mirror of https://github.com/proxmox/mirror_qemu
ppc: Fix coding style in helper.c
helper.c will be spilt by the next patches, fix style issues before that. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>master
Blue Swirl
Alexander Graf
parent
e5f17ac633
commit
4d5ea5e523
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@ -1,5 +1,5 @@
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/*
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* PowerPC emulation helpers for qemu.
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* PowerPC emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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@ -84,8 +84,9 @@ int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
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} else {
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exception = POWERPC_EXCP_DSI;
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error_code = 0x40000000;
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if (rw)
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if (rw) {
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error_code |= 0x02000000;
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}
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env->spr[SPR_DAR] = address;
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env->spr[SPR_DSISR] = error_code;
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}
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@ -160,8 +161,9 @@ static inline int pp_check(int key, int pp, int nx)
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break;
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}
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}
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if (nx == 0)
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if (nx == 0) {
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access |= PAGE_EXEC;
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}
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return access;
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}
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@ -171,26 +173,29 @@ static inline int check_prot(int prot, int rw, int access_type)
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int ret;
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if (access_type == ACCESS_CODE) {
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if (prot & PAGE_EXEC)
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if (prot & PAGE_EXEC) {
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ret = 0;
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else
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ret = -2;
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} else if (rw) {
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if (prot & PAGE_WRITE)
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ret = 0;
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else
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ret = -2;
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} else {
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if (prot & PAGE_READ)
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ret = 0;
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else
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ret = -2;
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}
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} else if (rw) {
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if (prot & PAGE_WRITE) {
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ret = 0;
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} else {
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ret = -2;
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}
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} else {
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if (prot & PAGE_READ) {
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ret = 0;
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} else {
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ret = -2;
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}
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}
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return ret;
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}
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static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
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static inline int pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type)
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{
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target_ulong ptem, mmask;
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@ -254,14 +259,14 @@ static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
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static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type)
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{
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return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
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return pte_check(ctx, 0, pte0, pte1, h, rw, type);
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}
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#if defined(TARGET_PPC64)
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static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type)
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{
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return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
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return pte_check(ctx, 1, pte0, pte1, h, rw, type);
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}
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#endif
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@ -291,8 +296,8 @@ static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
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}
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/* Software driven TLB helpers */
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static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, int way,
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int is_code)
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static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
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int way, int is_code)
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{
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int nr;
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@ -301,8 +306,9 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, int wa
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/* Select TLB way */
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nr += env->tlb_per_way * way;
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/* 6xx have separate TLBs for instructions and data */
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if (is_code && env->id_tlbs == 1)
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if (is_code && env->id_tlbs == 1) {
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nr += env->nb_tlb;
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}
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return nr;
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}
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@ -312,11 +318,12 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
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ppc6xx_tlb_t *tlb;
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int nr, max;
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//LOG_SWTLB("Invalidate all TLBs\n");
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/* LOG_SWTLB("Invalidate all TLBs\n"); */
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/* Invalidate all defined software TLB */
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max = env->nb_tlb;
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if (env->id_tlbs == 1)
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if (env->id_tlbs == 1) {
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max *= 2;
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}
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for (nr = 0; nr < max; nr++) {
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tlb = &env->tlb.tlb6[nr];
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pte_invalidate(&tlb->pte0);
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@ -324,7 +331,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
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tlb_flush(env, 1);
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}
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static inline void __ppc6xx_tlb_invalidate_virt(CPUPPCState *env,
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static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
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target_ulong eaddr,
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int is_code, int match_epn)
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{
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@ -352,7 +359,7 @@ static inline void __ppc6xx_tlb_invalidate_virt(CPUPPCState *env,
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static inline void ppc6xx_tlb_invalidate_virt(CPUPPCState *env,
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target_ulong eaddr, int is_code)
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{
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__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
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ppc6xx_tlb_invalidate_virt2(env, eaddr, is_code, 0);
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}
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void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way, int is_code,
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@ -366,7 +373,7 @@ void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
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LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
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" PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
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/* Invalidate any pending reference in QEMU for this virtual address */
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__ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
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ppc6xx_tlb_invalidate_virt2(env, EPN, is_code, 1);
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tlb->pte0 = pte0;
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tlb->pte1 = pte1;
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tlb->EPN = EPN;
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@ -436,8 +443,8 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
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}
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/* Perform BAT hit & translation */
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static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp, int *validp,
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int *protp, target_ulong *BATu,
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static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp,
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int *validp, int *protp, target_ulong *BATu,
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target_ulong *BATl)
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{
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target_ulong bl;
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@ -452,10 +459,11 @@ static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp, int *valid
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pp = *BATl & 0x00000003;
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if (pp != 0) {
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prot = PAGE_READ | PAGE_EXEC;
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if (pp == 0x2)
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if (pp == 0x2) {
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prot |= PAGE_WRITE;
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}
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}
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}
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*blp = bl;
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*validp = valid;
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*protp = prot;
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@ -475,10 +483,11 @@ static inline void bat_601_size_prot(CPUPPCState *env, target_ulong *blp,
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valid = (*BATl >> 6) & 1;
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if (valid) {
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pp = *BATu & 0x00000003;
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if (msr_pr == 0)
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if (msr_pr == 0) {
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key = (*BATu >> 3) & 1;
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else
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} else {
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key = (*BATu >> 2) & 1;
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}
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prot = pp_check(key, pp, 0);
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}
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*blp = bl;
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@ -486,8 +495,8 @@ static inline void bat_601_size_prot(CPUPPCState *env, target_ulong *blp,
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*protp = prot;
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}
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static inline int get_bat(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong virtual,
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int rw, int type)
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static inline int get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong virtual, int rw, int type)
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{
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target_ulong *BATlt, *BATut, *BATu, *BATl;
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target_ulong BEPIl, BEPIu, bl;
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@ -530,10 +539,11 @@ static inline int get_bat(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong virtual
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/* Compute access rights */
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ctx->prot = prot;
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ret = check_prot(ctx->prot, rw, type);
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if (ret == 0)
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if (ret == 0) {
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LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
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i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
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ctx->prot & PAGE_WRITE ? 'W' : '-');
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}
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break;
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}
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}
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@ -569,7 +579,7 @@ static inline target_phys_addr_t get_pteg_offset(CPUPPCState *env,
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}
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/* PTE table lookup */
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static inline int _find_pte(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h,
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static inline int find_pte2(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h,
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int rw, int type, int target_page_bits)
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{
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target_phys_addr_t pteg_off;
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@ -679,11 +689,12 @@ static inline int find_pte(CPUPPCState *env, mmu_ctx_t *ctx, int h, int rw,
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int type, int target_page_bits)
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{
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64)
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return _find_pte(env, ctx, 1, h, rw, type, target_page_bits);
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if (env->mmu_model & POWERPC_MMU_64) {
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return find_pte2(env, ctx, 1, h, rw, type, target_page_bits);
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}
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#endif
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return _find_pte(env, ctx, 0, h, rw, type, target_page_bits);
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return find_pte2(env, ctx, 0, h, rw, type, target_page_bits);
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}
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#if defined(TARGET_PPC64)
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@ -734,9 +745,10 @@ void ppc_slb_invalidate_all (CPUPPCState *env)
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do_invalidate = 1;
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}
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}
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if (do_invalidate)
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if (do_invalidate) {
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tlb_flush(env, 1);
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}
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}
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void ppc_slb_invalidate_one(CPUPPCState *env, uint64_t T0)
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{
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@ -909,21 +921,24 @@ static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
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ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
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if (ret < 0) {
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/* Secondary table lookup */
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if (eaddr != 0xEFFFFFFF)
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if (eaddr != 0xEFFFFFFF) {
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
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}
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ret2 = find_pte(env, ctx, 1, rw, type,
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target_page_bits);
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if (ret2 != -1)
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if (ret2 != -1) {
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ret = ret2;
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}
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}
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}
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#if defined(DUMP_PAGE_TABLES)
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if (qemu_log_enabled()) {
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target_phys_addr_t curaddr;
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uint32_t a0, a1, a2, a3;
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qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
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"\n", sdr, mask + 0x80);
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for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
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@ -945,6 +960,7 @@ static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
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}
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} else {
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target_ulong sr;
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LOG_MMU("direct store...\n");
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/* Direct-store segment : absolutely *BUGGY* for now */
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@ -1018,11 +1034,13 @@ int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
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" " TARGET_FMT_lx " %u %x\n", __func__, i, address, pid, tlb->EPN,
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mask, (uint32_t)tlb->PID, tlb->prot);
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/* Check PID */
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if (tlb->PID != 0 && tlb->PID != pid)
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if (tlb->PID != 0 && tlb->PID != pid) {
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return -1;
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}
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/* Check effective address */
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if ((address & mask) != tlb->EPN)
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if ((address & mask) != tlb->EPN) {
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return -1;
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}
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*raddrp = (tlb->RPN & mask) | (address & ~mask);
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#if (TARGET_PHYS_ADDR_BITS >= 36)
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if (ext) {
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@ -1080,8 +1098,9 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
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tlb = &env->tlb.tlbe[i];
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if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
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end = tlb->EPN + tlb->size;
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for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
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for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
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tlb_flush_page(env, page);
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}
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tlb->prot &= ~PAGE_VALID;
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break;
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}
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@ -1092,7 +1111,8 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
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}
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static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong address, int rw, int access_type)
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target_ulong address, int rw,
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int access_type)
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{
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ppcemb_tlb_t *tlb;
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target_phys_addr_t raddr;
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@ -1104,8 +1124,9 @@ static int mmu40x_get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx,
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb.tlbe[i];
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if (ppcemb_tlb_check(env, tlb, &raddr, address,
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env->spr[SPR_40x_PID], 0, i) < 0)
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env->spr[SPR_40x_PID], 0, i) < 0) {
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continue;
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}
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zsel = (tlb->attr >> 4) & 0xF;
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zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3;
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LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
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@ -1113,8 +1134,9 @@ static int mmu40x_get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx,
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/* Check execute enable bit */
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switch (zpr) {
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case 0x2:
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if (pr != 0)
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if (pr != 0) {
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goto check_perms;
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}
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/* No break here */
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case 0x3:
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/* All accesses granted */
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@ -1135,8 +1157,9 @@ static int mmu40x_get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx,
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/* Check from TLB entry */
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ctx->prot = tlb->prot;
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ret = check_prot(ctx->prot, rw, access_type);
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if (ret == -2)
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if (ret == -2) {
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env->spr[SPR_40x_ESR] = 0;
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}
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break;
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}
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if (ret >= 0) {
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@ -1167,7 +1190,7 @@ static inline int mmubooke_check_tlb (CPUPPCState *env, ppcemb_tlb_t *tlb,
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target_ulong address, int rw,
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int access_type, int i)
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{
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int ret, _prot;
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int ret, prot2;
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if (ppcemb_tlb_check(env, tlb, raddr, address,
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env->spr[SPR_BOOKE_PID],
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@ -1193,9 +1216,9 @@ static inline int mmubooke_check_tlb (CPUPPCState *env, ppcemb_tlb_t *tlb,
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found_tlb:
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if (msr_pr != 0) {
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_prot = tlb->prot & 0xF;
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prot2 = tlb->prot & 0xF;
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} else {
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_prot = (tlb->prot >> 4) & 0xF;
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prot2 = (tlb->prot >> 4) & 0xF;
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}
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/* Check the address space */
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@ -1205,13 +1228,13 @@ found_tlb:
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return -1;
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}
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*prot = _prot;
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if (_prot & PAGE_EXEC) {
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*prot = prot2;
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if (prot2 & PAGE_EXEC) {
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LOG_SWTLB("%s: good TLB!\n", __func__);
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return 0;
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}
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|
||||
LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, _prot);
|
||||
LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, prot2);
|
||||
ret = -3;
|
||||
} else {
|
||||
if (msr_dr != (tlb->attr & 1)) {
|
||||
|
|
@ -1219,13 +1242,13 @@ found_tlb:
|
|||
return -1;
|
||||
}
|
||||
|
||||
*prot = _prot;
|
||||
if ((!rw && _prot & PAGE_READ) || (rw && (_prot & PAGE_WRITE))) {
|
||||
*prot = prot2;
|
||||
if ((!rw && prot2 & PAGE_READ) || (rw && (prot2 & PAGE_WRITE))) {
|
||||
LOG_SWTLB("%s: found TLB!\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
LOG_SWTLB("%s: PAGE_READ/WRITE doesn't match: %x\n", __func__, _prot);
|
||||
LOG_SWTLB("%s: PAGE_READ/WRITE doesn't match: %x\n", __func__, prot2);
|
||||
ret = -2;
|
||||
}
|
||||
|
||||
|
|
@ -1285,7 +1308,8 @@ void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot)
|
|||
tlb_flush(env, 1);
|
||||
}
|
||||
|
||||
target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb)
|
||||
target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env,
|
||||
ppcmas_tlb_t *tlb)
|
||||
{
|
||||
int tlbm_size;
|
||||
|
||||
|
|
@ -1337,7 +1361,7 @@ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
|
|||
int access_type)
|
||||
{
|
||||
int ret;
|
||||
int _prot = 0;
|
||||
int prot2 = 0;
|
||||
|
||||
if (ppcmas_tlb_check(env, tlb, raddr, address,
|
||||
env->spr[SPR_BOOKE_PID]) >= 0) {
|
||||
|
|
@ -1363,23 +1387,23 @@ found_tlb:
|
|||
|
||||
if (msr_pr != 0) {
|
||||
if (tlb->mas7_3 & MAS3_UR) {
|
||||
_prot |= PAGE_READ;
|
||||
prot2 |= PAGE_READ;
|
||||
}
|
||||
if (tlb->mas7_3 & MAS3_UW) {
|
||||
_prot |= PAGE_WRITE;
|
||||
prot2 |= PAGE_WRITE;
|
||||
}
|
||||
if (tlb->mas7_3 & MAS3_UX) {
|
||||
_prot |= PAGE_EXEC;
|
||||
prot2 |= PAGE_EXEC;
|
||||
}
|
||||
} else {
|
||||
if (tlb->mas7_3 & MAS3_SR) {
|
||||
_prot |= PAGE_READ;
|
||||
prot2 |= PAGE_READ;
|
||||
}
|
||||
if (tlb->mas7_3 & MAS3_SW) {
|
||||
_prot |= PAGE_WRITE;
|
||||
prot2 |= PAGE_WRITE;
|
||||
}
|
||||
if (tlb->mas7_3 & MAS3_SX) {
|
||||
_prot |= PAGE_EXEC;
|
||||
prot2 |= PAGE_EXEC;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1390,13 +1414,13 @@ found_tlb:
|
|||
return -1;
|
||||
}
|
||||
|
||||
*prot = _prot;
|
||||
if (_prot & PAGE_EXEC) {
|
||||
*prot = prot2;
|
||||
if (prot2 & PAGE_EXEC) {
|
||||
LOG_SWTLB("%s: good TLB!\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, _prot);
|
||||
LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, prot2);
|
||||
ret = -3;
|
||||
} else {
|
||||
if (msr_dr != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
|
||||
|
|
@ -1404,13 +1428,13 @@ found_tlb:
|
|||
return -1;
|
||||
}
|
||||
|
||||
*prot = _prot;
|
||||
if ((!rw && _prot & PAGE_READ) || (rw && (_prot & PAGE_WRITE))) {
|
||||
*prot = prot2;
|
||||
if ((!rw && prot2 & PAGE_READ) || (rw && (prot2 & PAGE_WRITE))) {
|
||||
LOG_SWTLB("%s: found TLB!\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
LOG_SWTLB("%s: PAGE_READ/WRITE doesn't match: %x\n", __func__, _prot);
|
||||
LOG_SWTLB("%s: PAGE_READ/WRITE doesn't match: %x\n", __func__, prot2);
|
||||
ret = -2;
|
||||
}
|
||||
|
||||
|
|
@ -1521,7 +1545,8 @@ static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
|
|||
int i;
|
||||
|
||||
cpu_fprintf(f, "\nTLB%d:\n", tlbn);
|
||||
cpu_fprintf(f, "Effective Physical Size TID TS SRWX URWX WIMGE U0123\n");
|
||||
cpu_fprintf(f, "Effective Physical Size TID TS SRWX"
|
||||
" URWX WIMGE U0123\n");
|
||||
|
||||
entry = &env->tlb.tlbm[offset];
|
||||
for (i = 0; i < tlbsize; i++, entry++) {
|
||||
|
|
@ -1537,7 +1562,8 @@ static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
|
|||
ea = entry->mas2 & ~(size - 1);
|
||||
pa = entry->mas7_3 & ~(size - 1);
|
||||
|
||||
cpu_fprintf(f, "0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
|
||||
cpu_fprintf(f, "0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c"
|
||||
"U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
|
||||
(uint64_t)ea, (uint64_t)pa,
|
||||
book3e_tsize_to_str[tsize],
|
||||
(entry->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT,
|
||||
|
|
@ -1721,8 +1747,9 @@ int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
|||
case POWERPC_MMU_SOFT_6xx:
|
||||
case POWERPC_MMU_SOFT_74xx:
|
||||
/* Try to find a BAT */
|
||||
if (env->nb_BATs != 0)
|
||||
if (env->nb_BATs != 0) {
|
||||
ret = get_bat(env, ctx, eaddr, rw, access_type);
|
||||
}
|
||||
#if defined(TARGET_PPC64)
|
||||
case POWERPC_MMU_620:
|
||||
case POWERPC_MMU_64B:
|
||||
|
|
@ -1770,8 +1797,9 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUPPCState *env, target_ulong addr)
|
|||
{
|
||||
mmu_ctx_t ctx;
|
||||
|
||||
if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0))
|
||||
if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return ctx.raddr & TARGET_PAGE_MASK;
|
||||
}
|
||||
|
|
@ -1966,10 +1994,11 @@ int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
|
|||
env->exception_index = POWERPC_EXCP_DTLB;
|
||||
env->error_code = 0;
|
||||
env->spr[SPR_40x_DEAR] = address;
|
||||
if (rw)
|
||||
if (rw) {
|
||||
env->spr[SPR_40x_ESR] = 0x00800000;
|
||||
else
|
||||
} else {
|
||||
env->spr[SPR_40x_ESR] = 0x00000000;
|
||||
}
|
||||
break;
|
||||
case POWERPC_MMU_32B:
|
||||
case POWERPC_MMU_601:
|
||||
|
|
@ -1981,10 +2010,11 @@ int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
|
|||
env->exception_index = POWERPC_EXCP_DSI;
|
||||
env->error_code = 0;
|
||||
env->spr[SPR_DAR] = address;
|
||||
if (rw == 1)
|
||||
if (rw == 1) {
|
||||
env->spr[SPR_DSISR] = 0x42000000;
|
||||
else
|
||||
} else {
|
||||
env->spr[SPR_DSISR] = 0x40000000;
|
||||
}
|
||||
break;
|
||||
case POWERPC_MMU_MPC8xx:
|
||||
/* XXX: TODO */
|
||||
|
|
@ -2045,20 +2075,22 @@ int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
|
|||
env->exception_index = POWERPC_EXCP_DSI;
|
||||
env->error_code = 0;
|
||||
env->spr[SPR_DAR] = address;
|
||||
if (rw == 1)
|
||||
if (rw == 1) {
|
||||
env->spr[SPR_DSISR] = 0x06000000;
|
||||
else
|
||||
} else {
|
||||
env->spr[SPR_DSISR] = 0x04000000;
|
||||
}
|
||||
break;
|
||||
case ACCESS_EXT:
|
||||
/* eciwx or ecowx */
|
||||
env->exception_index = POWERPC_EXCP_DSI;
|
||||
env->error_code = 0;
|
||||
env->spr[SPR_DAR] = address;
|
||||
if (rw == 1)
|
||||
if (rw == 1) {
|
||||
env->spr[SPR_DSISR] = 0x06100000;
|
||||
else
|
||||
} else {
|
||||
env->spr[SPR_DSISR] = 0x04100000;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
printf("DSI: invalid exception (%d)\n", ret);
|
||||
|
|
@ -2077,10 +2109,11 @@ int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
|
|||
env->error_code = 0;
|
||||
env->spr[SPR_DAR] = address;
|
||||
/* XXX: this might be incorrect */
|
||||
if (rw == 1)
|
||||
if (rw == 1) {
|
||||
env->spr[SPR_DSISR] = 0x42000000;
|
||||
else
|
||||
} else {
|
||||
env->spr[SPR_DSISR] = 0x40000000;
|
||||
}
|
||||
} else {
|
||||
env->exception_index = POWERPC_EXCP_DSEG;
|
||||
env->error_code = 0;
|
||||
|
|
@ -2112,8 +2145,9 @@ static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
|
|||
end = base + mask + 0x00020000;
|
||||
LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
|
||||
TARGET_FMT_lx ")\n", base, end, mask);
|
||||
for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
||||
for (page = base; page != end; page += TARGET_PAGE_SIZE) {
|
||||
tlb_flush_page(env, page);
|
||||
}
|
||||
LOG_BATS("Flush done\n");
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2224,8 +2258,9 @@ void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
|
|||
#endif
|
||||
}
|
||||
#if defined(FLUSH_ALL_TLBS)
|
||||
if (do_inval)
|
||||
if (do_inval) {
|
||||
tlb_flush(env, 1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
@ -2261,8 +2296,9 @@ void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
|
|||
env->IBAT[1][nr] = value;
|
||||
env->DBAT[1][nr] = value;
|
||||
#if defined(FLUSH_ALL_TLBS)
|
||||
if (do_inval)
|
||||
if (do_inval) {
|
||||
tlb_flush(env, 1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
@ -2317,8 +2353,9 @@ void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
|
|||
case POWERPC_MMU_SOFT_6xx:
|
||||
case POWERPC_MMU_SOFT_74xx:
|
||||
ppc6xx_tlb_invalidate_virt(env, addr, 0);
|
||||
if (env->id_tlbs == 1)
|
||||
if (env->id_tlbs == 1) {
|
||||
ppc6xx_tlb_invalidate_virt(env, addr, 1);
|
||||
}
|
||||
break;
|
||||
case POWERPC_MMU_SOFT_4xx:
|
||||
case POWERPC_MMU_SOFT_4xx_Z:
|
||||
|
|
@ -2427,7 +2464,7 @@ void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
|
|||
#if defined(TARGET_PPC64)
|
||||
target_ulong ppc_load_sr(CPUPPCState *env, int slb_nr)
|
||||
{
|
||||
// XXX
|
||||
/* XXX */
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2465,9 +2502,10 @@ void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
|
|||
/* Invalidate 256 MB of virtual memory */
|
||||
page = (16 << 20) * srnum;
|
||||
end = page + (16 << 20);
|
||||
for (; page != end; page += TARGET_PAGE_SIZE)
|
||||
for (; page != end; page += TARGET_PAGE_SIZE) {
|
||||
tlb_flush_page(env, page);
|
||||
}
|
||||
}
|
||||
#else
|
||||
tlb_flush(env, 1);
|
||||
#endif
|
||||
|
|
@ -2602,23 +2640,27 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
case POWERPC_EXCP_DSI: /* Data storage exception */
|
||||
LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
|
||||
"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_ISI: /* Instruction storage exception */
|
||||
LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
|
||||
"\n", msr, env->nip);
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
msr |= env->error_code;
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_EXTERNAL: /* External input */
|
||||
if (lpes0 == 1)
|
||||
if (lpes0 == 1) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_ALIGN: /* Alignment exception */
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
/* XXX: this is false */
|
||||
/* Get rS/rD and rA from faulting opcode */
|
||||
env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
|
||||
|
|
@ -2632,29 +2674,34 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
env->error_code = 0;
|
||||
return;
|
||||
}
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
msr |= 0x00100000;
|
||||
if (msr_fe0 == msr_fe1)
|
||||
if (msr_fe0 == msr_fe1) {
|
||||
goto store_next;
|
||||
}
|
||||
msr |= 0x00010000;
|
||||
break;
|
||||
case POWERPC_EXCP_INVAL:
|
||||
LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
msr |= 0x00080000;
|
||||
env->spr[SPR_BOOKE_ESR] = ESR_PIL;
|
||||
break;
|
||||
case POWERPC_EXCP_PRIV:
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
msr |= 0x00040000;
|
||||
env->spr[SPR_BOOKE_ESR] = ESR_PPR;
|
||||
break;
|
||||
case POWERPC_EXCP_TRAP:
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
msr |= 0x00020000;
|
||||
env->spr[SPR_BOOKE_ESR] = ESR_PTR;
|
||||
break;
|
||||
|
|
@ -2666,8 +2713,9 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
}
|
||||
goto store_current;
|
||||
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
goto store_current;
|
||||
case POWERPC_EXCP_SYSCALL: /* System call exception */
|
||||
dump_syscall(env);
|
||||
|
|
@ -2676,14 +2724,16 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
cpu_ppc_hypercall(env);
|
||||
return;
|
||||
}
|
||||
if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
|
||||
if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
|
||||
goto store_current;
|
||||
case POWERPC_EXCP_DECR: /* Decrementer exception */
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
|
||||
/* FIT on 4xx */
|
||||
|
|
@ -2758,12 +2808,14 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
}
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_DSEG: /* Data segment exception */
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_ISEG: /* Instruction segment exception */
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
|
||||
srr0 = SPR_HSRR0;
|
||||
|
|
@ -2772,8 +2824,9 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_TRACE: /* Trace exception */
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
|
||||
srr0 = SPR_HSRR0;
|
||||
|
|
@ -2800,8 +2853,9 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
goto store_current;
|
||||
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
|
||||
LOG_EXCP("PIT exception\n");
|
||||
|
|
@ -2820,8 +2874,9 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
"is not implemented yet !\n");
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
|
||||
if (lpes1 == 0) /* XXX: check this */
|
||||
if (lpes1 == 0) { /* XXX: check this */
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
switch (excp_model) {
|
||||
case POWERPC_EXCP_602:
|
||||
case POWERPC_EXCP_603:
|
||||
|
|
@ -2838,8 +2893,9 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
}
|
||||
break;
|
||||
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
|
||||
if (lpes1 == 0) /* XXX: check this */
|
||||
if (lpes1 == 0) { /* XXX: check this */
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
switch (excp_model) {
|
||||
case POWERPC_EXCP_602:
|
||||
case POWERPC_EXCP_603:
|
||||
|
|
@ -2856,8 +2912,9 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
}
|
||||
break;
|
||||
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
|
||||
if (lpes1 == 0) /* XXX: check this */
|
||||
if (lpes1 == 0) { /* XXX: check this */
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
switch (excp_model) {
|
||||
case POWERPC_EXCP_602:
|
||||
case POWERPC_EXCP_603:
|
||||
|
|
@ -2877,16 +2934,18 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
const char *es;
|
||||
target_ulong *miss, *cmp;
|
||||
int en;
|
||||
|
||||
if (excp == POWERPC_EXCP_IFTLB) {
|
||||
es = "I";
|
||||
en = 'I';
|
||||
miss = &env->spr[SPR_IMISS];
|
||||
cmp = &env->spr[SPR_ICMP];
|
||||
} else {
|
||||
if (excp == POWERPC_EXCP_DLTLB)
|
||||
if (excp == POWERPC_EXCP_DLTLB) {
|
||||
es = "DL";
|
||||
else
|
||||
} else {
|
||||
es = "DS";
|
||||
}
|
||||
en = 'D';
|
||||
miss = &env->spr[SPR_DMISS];
|
||||
cmp = &env->spr[SPR_DCMP];
|
||||
|
|
@ -2910,16 +2969,18 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
const char *es;
|
||||
target_ulong *miss, *cmp;
|
||||
int en;
|
||||
|
||||
if (excp == POWERPC_EXCP_IFTLB) {
|
||||
es = "I";
|
||||
en = 'I';
|
||||
miss = &env->spr[SPR_TLBMISS];
|
||||
cmp = &env->spr[SPR_PTEHI];
|
||||
} else {
|
||||
if (excp == POWERPC_EXCP_DLTLB)
|
||||
if (excp == POWERPC_EXCP_DLTLB) {
|
||||
es = "DL";
|
||||
else
|
||||
} else {
|
||||
es = "DS";
|
||||
}
|
||||
en = 'D';
|
||||
miss = &env->spr[SPR_TLBMISS];
|
||||
cmp = &env->spr[SPR_PTEHI];
|
||||
|
|
@ -2959,8 +3020,9 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
"is not implemented yet !\n");
|
||||
goto store_next;
|
||||
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
|
||||
if (lpes1 == 0)
|
||||
if (lpes1 == 0) {
|
||||
new_msr |= (target_ulong)MSR_HVB;
|
||||
}
|
||||
/* XXX: TODO */
|
||||
cpu_abort(env,
|
||||
"Performance counter exception is not implemented yet !\n");
|
||||
|
|
@ -3005,13 +3067,16 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
|
|||
/* Save MSR */
|
||||
env->spr[srr1] = msr;
|
||||
/* If any alternate SRR register are defined, duplicate saved values */
|
||||
if (asrr0 != -1)
|
||||
if (asrr0 != -1) {
|
||||
env->spr[asrr0] = env->spr[srr0];
|
||||
if (asrr1 != -1)
|
||||
}
|
||||
if (asrr1 != -1) {
|
||||
env->spr[asrr1] = env->spr[srr1];
|
||||
}
|
||||
/* If we disactivated any translation, flush TLBs */
|
||||
if (msr & ((1 << MSR_IR) | (1 << MSR_DR)))
|
||||
if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
|
||||
tlb_flush(env, 1);
|
||||
}
|
||||
|
||||
if (msr_ile) {
|
||||
new_msr |= (target_ulong)1 << MSR_LE;
|
||||
|
|
@ -3193,8 +3258,9 @@ PowerPCCPU *cpu_ppc_init(const char *cpu_model)
|
|||
const ppc_def_t *def;
|
||||
|
||||
def = cpu_ppc_find_by_name(cpu_model);
|
||||
if (!def)
|
||||
if (!def) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cpu = POWERPC_CPU(object_new(TYPE_POWERPC_CPU));
|
||||
env = &cpu->env;
|
||||
|
|
|
|||
Loading…
Reference in New Issue