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hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4 

The GICv4 defines a new in-guest-memory table for the ITS: this is
the vPE table.  Implement the new GITS_BASER2 register which the
guest uses to tell the ITS where the vPE table is located, including
the decode of the register fields into the TableDesc structure which
we do for the GITS_BASER<n> when the guest enables the ITS.

We guard provision of the new register with the its_feature_virtual()
function, which does a check of the GITS_TYPER.Virtual bit which
indicates presence of ITS support for virtual LPIs.  Since this bit
is currently always zero, GICv4-specific features will not be
accessible to the guest yet.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-8-peter.maydell@linaro.org
master
Peter Maydell 2022-04-08 15:15:16 +01:00
parent c3c9a09073
commit 50d84584d3
3 changed files with 42 additions and 0 deletions
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25
hw/intc/arm_gicv3_its.c
View File

@ -79,6 +79,12 @@ typedef enum ItsCmdResult {
CMD_CONTINUE = 1,
} ItsCmdResult;
/* True if the ITS supports the GICv4 virtual LPI feature */
static bool its_feature_virtual(GICv3ITSState *s)
{
return s->typer & R_GITS_TYPER_VIRTUAL_MASK;
}
static inline bool intid_in_lpi_range(uint32_t id)
{
return id >= GICV3_LPI_INTID_START &&
@ -946,6 +952,15 @@ static void extract_table_params(GICv3ITSState *s)
idbits = 16;
}
break;
case GITS_BASER_TYPE_VPE:
td = &s->vpet;
/*
* For QEMU vPEIDs are always 16 bits. (GICv4.1 allows an
* implementation to implement fewer bits and report this
* via GICD_TYPER2.)
*/
idbits = 16;
break;
default:
/*
* GITS_BASER<n>.TYPE is read-only, so GITS_BASER_RO_MASK
@ -1425,6 +1440,7 @@ static void gicv3_its_reset(DeviceState *dev)
/*
* setting GITS_BASER0.Type = 0b001 (Device)
* GITS_BASER1.Type = 0b100 (Collection Table)
* GITS_BASER2.Type = 0b010 (vPE) for GICv4 and later
* GITS_BASER<n>.Type,where n = 3 to 7 are 0b00 (Unimplemented)
* GITS_BASER<0,1>.Page_Size = 64KB
* and default translation table entry size to 16 bytes
@ -1442,6 +1458,15 @@ static void gicv3_its_reset(DeviceState *dev)
GITS_BASER_PAGESIZE_64K);
s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, ENTRYSIZE,
GITS_CTE_SIZE - 1);
if (its_feature_virtual(s)) {
s->baser[2] = FIELD_DP64(s->baser[2], GITS_BASER, TYPE,
GITS_BASER_TYPE_VPE);
s->baser[2] = FIELD_DP64(s->baser[2], GITS_BASER, PAGESIZE,
GITS_BASER_PAGESIZE_64K);
s->baser[2] = FIELD_DP64(s->baser[2], GITS_BASER, ENTRYSIZE,
GITS_VPE_SIZE - 1);
}
}
static void gicv3_its_post_load(GICv3ITSState *s)

16
hw/intc/gicv3_internal.h
View File

@ -280,6 +280,7 @@ FIELD(GITS_CTLR, ENABLED, 0, 1)
FIELD(GITS_CTLR, QUIESCENT, 31, 1)
FIELD(GITS_TYPER, PHYSICAL, 0, 1)
FIELD(GITS_TYPER, VIRTUAL, 1, 1)
FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4)
FIELD(GITS_TYPER, IDBITS, 8, 5)
FIELD(GITS_TYPER, DEVBITS, 13, 5)
@ -298,6 +299,7 @@ FIELD(GITS_TYPER, CIL, 36, 1)
#define GITS_BASER_PAGESIZE_64K 2
#define GITS_BASER_TYPE_DEVICE 1ULL
#define GITS_BASER_TYPE_VPE 2ULL
#define GITS_BASER_TYPE_COLLECTION 4ULL
#define GITS_PAGE_SIZE_4K 0x1000
@ -419,6 +421,20 @@ FIELD(DTE, ITTADDR, 6, 44)
FIELD(CTE, VALID, 0, 1)
FIELD(CTE, RDBASE, 1, RDBASE_PROCNUM_LENGTH)
/*
* 8 bytes VPE table entry size:
* Valid = 1 bit, VPTsize = 5 bits, VPTaddr = 36 bits, RDbase = 16 bits
*
* Field sizes for Valid and size are mandated; field sizes for RDbase
* and VPT_addr are IMPDEF.
*/
#define GITS_VPE_SIZE 0x8ULL
FIELD(VTE, VALID, 0, 1)
FIELD(VTE, VPTSIZE, 1, 5)
FIELD(VTE, VPTADDR, 6, 36)
FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH)
/* Special interrupt IDs */
#define INTID_SECURE 1020
#define INTID_NONSECURE 1021

1
include/hw/intc/arm_gicv3_its_common.h
View File

@ -78,6 +78,7 @@ struct GICv3ITSState {
TableDesc dt;
TableDesc ct;
TableDesc vpet;
CmdQDesc cq;
Error *migration_blocker;