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target/riscv: Remove sideleg and sedeleg 

sideleg and sedeleg csrs are not part of riscv isa spec
anymore, these csrs were part of N extension which
is removed from the riscv isa specification.

These commits removed all traces of these csrs from
riscv spec (https://github.com/riscv/riscv-isa-manual) -

commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)")
commit b6cade07034d ("Remove N extension chapter for now")

Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
master
Rahul Pathak 2022-08-24 20:22:55 +05:30 committed by Alistair Francis
parent 0c2d467191
commit 513eb437ae
2 changed files with 0 additions and 4 deletions
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2
disas/riscv.c
View File

@ -1304,8 +1304,6 @@ static const char *csr_name(int csrno)
case 0x0043: return "utval";
case 0x0044: return "uip";
case 0x0100: return "sstatus";
case 0x0102: return "sedeleg";
case 0x0103: return "sideleg";
case 0x0104: return "sie";
case 0x0105: return "stvec";
case 0x0106: return "scounteren";

2
target/riscv/cpu_bits.h
View File

@ -190,8 +190,6 @@
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
#define CSR_SEDELEG 0x102
#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106