vitalif
/
mirror_qemu
mirror of https://github.com/proxmox/mirror_qemu
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/microblaze: Add the ill-opcode-exception property 

Add the ill-opcode-exception property to control if illegal
instructions will raise exceptions.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
master
Edgar E. Iglesias 2019-10-30 13:55:08 +01:00
parent 1ee1bd28fc
commit 5143fdf36f
3 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target/microblaze/cpu.c
View File

@ -207,6 +207,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
PVR2_DOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.iopb_bus_exception ?
PVR2_IOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.illegal_opcode_exception ?
PVR2_ILL_OPCODE_EXC_MASK : 0) |
(cpu->cfg.opcode_0_illegal ?
PVR2_OPCODE_0x0_ILL_MASK : 0);
@ -276,6 +278,8 @@ static Property mb_properties[] = {
/* Enables bus exceptions on failed instruction fetches. */
DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
cfg.iopb_bus_exception, false),
DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
cfg.illegal_opcode_exception, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),

1
target/microblaze/cpu.h
View File

@ -303,6 +303,7 @@ struct MicroBlazeCPU {
bool endi;
bool dopb_bus_exception;
bool iopb_bus_exception;
bool illegal_opcode_exception;
bool opcode_0_illegal;
char *version;
uint8_t pvr;

2
target/microblaze/translate.c
View File

@ -185,7 +185,7 @@ static void write_carryi(DisasContext *dc, bool carry)
static bool trap_illegal(DisasContext *dc, bool cond)
{
if (cond && (dc->tb_flags & MSR_EE_FLAG)
&& (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
&& dc->cpu->cfg.illegal_opcode_exception) {
tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}