mirror of https://github.com/proxmox/mirror_qemu
target-arm: A64: Implement scalar saturating narrow ops
This completes the set of integer narrowing saturating ops including: SQXTN, SQXTN2 SQXTUN, SQXTUN2 UQXTN, UQXTN2 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-23-git-send-email-peter.maydell@linaro.orgmaster
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8b092ca9ef
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5201c13654
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@ -7200,7 +7200,8 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
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tcg_temp_free_ptr(fpst);
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}
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static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q,
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static void handle_2misc_narrow(DisasContext *s, bool scalar,
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int opcode, bool u, bool is_q,
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int size, int rn, int rd)
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{
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/* Handle 2-reg-misc ops which are narrowing (so each 2*size element
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@ -7209,13 +7210,22 @@ static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q,
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int pass;
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TCGv_i32 tcg_res[2];
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int destelt = is_q ? 2 : 0;
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int passes = scalar ? 1 : 2;
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for (pass = 0; pass < 2; pass++) {
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if (scalar) {
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tcg_res[1] = tcg_const_i32(0);
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}
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for (pass = 0; pass < passes; pass++) {
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TCGv_i64 tcg_op = tcg_temp_new_i64();
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NeonGenNarrowFn *genfn = NULL;
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NeonGenNarrowEnvFn *genenvfn = NULL;
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if (scalar) {
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read_vec_element(s, tcg_op, rn, pass, size + 1);
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} else {
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read_vec_element(s, tcg_op, rn, pass, MO_64);
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}
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tcg_res[pass] = tcg_temp_new_i32();
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switch (opcode) {
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@ -7323,6 +7333,19 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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return;
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}
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break;
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case 0x12: /* SQXTUN */
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if (u) {
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unallocated_encoding(s);
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return;
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}
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/* fall through */
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case 0x14: /* SQXTN, UQXTN */
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if (size == 3) {
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unallocated_encoding(s);
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return;
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}
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handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd);
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return;
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case 0xc ... 0xf:
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case 0x16 ... 0x1d:
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case 0x1f:
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@ -7379,8 +7402,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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default:
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/* Other categories of encoding in this class:
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* + SUQADD/USQADD/SQABS/SQNEG : size 8, 16, 32 or 64
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* + SQXTN/SQXTN2/SQXTUN/SQXTUN2/UQXTN/UQXTN2:
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* narrowing saturate ops: size 64/32/16 -> 32/16/8
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*/
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unsupported_encoding(s, insn);
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return;
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@ -9096,7 +9117,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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unallocated_encoding(s);
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return;
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}
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handle_2misc_narrow(s, opcode, u, is_q, size, rn, rd);
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handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
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return;
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case 0x4: /* CLS, CLZ */
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if (size == 3) {
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@ -9227,7 +9248,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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/* handle_2misc_narrow does a 2*size -> size operation, but these
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* instructions encode the source size rather than dest size.
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*/
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handle_2misc_narrow(s, opcode, 0, is_q, size - 1, rn, rd);
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handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd);
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return;
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case 0x17: /* FCVTL, FCVTL2 */
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handle_2misc_widening(s, opcode, is_q, size, rn, rd);
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