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Merge branch 'xenfv-kvm-15' of git://git.infradead.org/users/dwmw2/qemu into HEAD 

This adds support for emulating Xen under Linux/KVM, based on kernel
patches which have been present since Linux v5.12. As with the kernel
support, it's derived from work started by João Martins of Oracle in
2018.

This series just adds the basic platform support — CPUID, hypercalls,
event channels, a stub of XenStore.

A full single-tenant internal implementation of XenStore, and patches
to make QEMU's Xen PV drivers work with this Xen emulation, are waiting
in the wings to be submitted in a follow-on patch series.

As noted in the documentation, it's enabled by setting the xen-version
property on the KVM accelerator, e.g.:

 qemu-system-x86_64 -serial mon:stdio -M q35 -display none -m 1G -smp 2 \
    -accel kvm,xen-version=0x4000e,kernel-irqchip=split \
    -kernel vmlinuz-6.0.7-301.fc37.x86_64 \
    -append "console=ttyS0 root=/dev/sda1" \
    -drive file=/var/lib/libvirt/images/fedora28.qcow2,if=none,id=disk \
    -device ahci,id=ahci -device ide-hd,drive=disk,bus=ahci.0

Even before this was merged, we've already been using it to find and fix
bugs in the Linux kernel Xen guest support:

https://lore.kernel.org/all/4bffa69a949bfdc92c4a18e5a1c3cbb3b94a0d32.camel@infradead.org/
https://lore.kernel.org/all/871qnunycr.ffs@tglx/

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
master
Paolo Bonzini 2023-03-01 15:02:13 +01:00
parent d31d240479 79807f3e6b
commit 526947e496
243 changed files with 15638 additions and 2170 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
MAINTAINERS
View File

@ -123,6 +123,7 @@ M: Richard Henderson <richard.henderson@linaro.org>
R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: softmmu/cpus.c
F: softmmu/watchpoint.c
F: cpus-common.c
F: page-vary.c
F: page-vary-common.c
@ -1679,6 +1680,7 @@ F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
F: hw/acpi/ich9*.c
F: include/hw/acpi/ich9*.h
F: include/hw/southbridge/ich9.h
F: include/hw/southbridge/piix.h
F: hw/isa/apm.c
F: include/hw/isa/apm.h
@ -1711,6 +1713,7 @@ F: include/hw/char/parallel.h
F: include/hw/dma/i8257.h
F: include/hw/i2c/pm_smbus.h
F: include/hw/input/i8042.h
F: include/hw/intc/ioapic*
F: include/hw/isa/i8259_internal.h
F: include/hw/isa/superio.h
F: include/hw/timer/hpet.h
@ -1795,7 +1798,7 @@ F: hw/misc/edu.c
IDE
M: John Snow <jsnow@redhat.com>
L: qemu-block@nongnu.org
S: Supported
S: Odd Fixes
F: include/hw/ide.h
F: include/hw/ide/
F: hw/ide/
@ -1820,7 +1823,7 @@ T: git https://github.com/cminyard/qemu.git master-ipmi-rebase
Floppy
M: John Snow <jsnow@redhat.com>
L: qemu-block@nongnu.org
S: Supported
S: Odd Fixes
F: hw/block/fdc.c
F: hw/block/fdc-internal.h
F: hw/block/fdc-isa.c
@ -3239,6 +3242,7 @@ S: Supported
F: replay/*
F: block/blkreplay.c
F: net/filter-replay.c
F: include/exec/replay-core.h
F: include/sysemu/replay.h
F: docs/devel/replay.rst
F: docs/system/replay.rst

11
accel/kvm/kvm-all.c
View File

@ -2361,13 +2361,13 @@ static int kvm_init(MachineState *ms)
static const char upgrade_note[] =
"Please upgrade to at least kernel 2.6.29 or recent kvm-kmod\n"
"(see http://sourceforge.net/projects/kvm).\n";
struct {
const struct {
const char *name;
int num;
} num_cpus[] = {
{ "SMP", ms->smp.cpus },
{ "hotpluggable", ms->smp.max_cpus },
{ NULL, }
{ /* end of list */ }
}, *nc = num_cpus;
int soft_vcpus_limit, hard_vcpus_limit;
KVMState *s;
@ -3305,7 +3305,7 @@ bool kvm_supports_guest_debug(void)
return kvm_has_guest_debug;
}
int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len)
int kvm_insert_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len)
{
struct kvm_sw_breakpoint *bp;
int err;
@ -3343,7 +3343,7 @@ int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len)
return 0;
}
int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len)
int kvm_remove_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len)
{
struct kvm_sw_breakpoint *bp;
int err;
@ -3703,6 +3703,9 @@ static void kvm_accel_instance_init(Object *obj)
s->kvm_dirty_ring_size = 0;
s->notify_vmexit = NOTIFY_VMEXIT_OPTION_RUN;
s->notify_window = 0;
s->xen_version = 0;
s->xen_gnttab_max_frames = 64;
s->xen_evtchn_max_pirq = 256;
}
/**

4
accel/kvm/kvm-cpus.h
View File

@ -19,8 +19,8 @@ void kvm_cpu_synchronize_post_reset(CPUState *cpu);
void kvm_cpu_synchronize_post_init(CPUState *cpu);
void kvm_cpu_synchronize_pre_loadvm(CPUState *cpu);
bool kvm_supports_guest_debug(void);
int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len);
int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len);
int kvm_insert_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len);
int kvm_remove_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len);
void kvm_remove_all_breakpoints(CPUState *cpu);
#endif /* KVM_CPUS_H */

91
accel/tcg/cpu-exec.c
View File

@ -20,7 +20,6 @@
#include "qemu/osdep.h"
#include "qemu/qemu-print.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-machine.h"
#include "qapi/type-helpers.h"
#include "hw/core/tcg-cpu-ops.h"
#include "trace.h"
@ -28,7 +27,6 @@
#include "exec/exec-all.h"
#include "tcg/tcg.h"
#include "qemu/atomic.h"
#include "qemu/timer.h"
#include "qemu/rcu.h"
#include "exec/log.h"
#include "qemu/main-loop.h"
@ -38,7 +36,7 @@
#include "sysemu/cpus.h"
#include "exec/cpu-all.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
#include "sysemu/tcg.h"
#include "exec/helper-proto.h"
#include "tb-jmp-cache.h"
@ -64,8 +62,8 @@ typedef struct SyncClocks {
#define MAX_DELAY_PRINT_RATE 2000000000LL
#define MAX_NB_PRINTS 100
static int64_t max_delay;
static int64_t max_advance;
int64_t max_delay;
int64_t max_advance;
static void align_clocks(SyncClocks *sc, CPUState *cpu)
{
@ -1072,86 +1070,3 @@ void tcg_exec_unrealizefn(CPUState *cpu)
tlb_destroy(cpu);
g_free_rcu(cpu->tb_jmp_cache, rcu);
}
#ifndef CONFIG_USER_ONLY
static void dump_drift_info(GString *buf)
{
if (!icount_enabled()) {
return;
}
g_string_append_printf(buf, "Host - Guest clock %"PRIi64" ms\n",
(cpu_get_clock() - icount_get()) / SCALE_MS);
if (icount_align_option) {
g_string_append_printf(buf, "Max guest delay %"PRIi64" ms\n",
-max_delay / SCALE_MS);
g_string_append_printf(buf, "Max guest advance %"PRIi64" ms\n",
max_advance / SCALE_MS);
} else {
g_string_append_printf(buf, "Max guest delay NA\n");
g_string_append_printf(buf, "Max guest advance NA\n");
}
}
HumanReadableText *qmp_x_query_jit(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
if (!tcg_enabled()) {
error_setg(errp, "JIT information is only available with accel=tcg");
return NULL;
}
dump_exec_info(buf);
dump_drift_info(buf);
return human_readable_text_from_str(buf);
}
HumanReadableText *qmp_x_query_opcount(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
if (!tcg_enabled()) {
error_setg(errp, "Opcode count information is only available with accel=tcg");
return NULL;
}
tcg_dump_op_count(buf);
return human_readable_text_from_str(buf);
}
#ifdef CONFIG_PROFILER
int64_t dev_time;
HumanReadableText *qmp_x_query_profile(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
static int64_t last_cpu_exec_time;
int64_t cpu_exec_time;
int64_t delta;
cpu_exec_time = tcg_cpu_exec_time();
delta = cpu_exec_time - last_cpu_exec_time;
g_string_append_printf(buf, "async time %" PRId64 " (%0.3f)\n",
dev_time, dev_time / (double)NANOSECONDS_PER_SECOND);
g_string_append_printf(buf, "qemu time %" PRId64 " (%0.3f)\n",
delta, delta / (double)NANOSECONDS_PER_SECOND);
last_cpu_exec_time = cpu_exec_time;
dev_time = 0;
return human_readable_text_from_str(buf);
}
#else
HumanReadableText *qmp_x_query_profile(Error **errp)
{
error_setg(errp, "Internal profiler not compiled");
return NULL;
}
#endif
#endif /* !CONFIG_USER_ONLY */

14
accel/tcg/hmp.c
View File

@ -1,14 +0,0 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-machine.h"
#include "exec/exec-all.h"
#include "monitor/monitor.h"
static void hmp_tcg_register(void)
{
monitor_register_hmp_info_hrt("jit", qmp_x_query_jit);
monitor_register_hmp_info_hrt("opcount", qmp_x_query_opcount);
}
type_init(hmp_tcg_register);

3
accel/tcg/internal.h
View File

@ -64,4 +64,7 @@ static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb)
#endif
}
extern int64_t max_delay;
extern int64_t max_advance;
#endif /* ACCEL_TCG_INTERNAL_H */

2
accel/tcg/meson.build
View File

@ -18,7 +18,7 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
'hmp.c',
'monitor.c',
))
tcg_module_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(

106
accel/tcg/monitor.c Normal file
View File

@ -0,0 +1,106 @@
/*
* SPDX-License-Identifier: LGPL-2.1-or-later
*
* QEMU TCG monitor
*
* Copyright (c) 2003-2005 Fabrice Bellard
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qapi/type-helpers.h"
#include "qapi/qapi-commands-machine.h"
#include "monitor/monitor.h"
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/tcg.h"
#include "internal.h"
static void dump_drift_info(GString *buf)
{
if (!icount_enabled()) {
return;
}
g_string_append_printf(buf, "Host - Guest clock %"PRIi64" ms\n",
(cpu_get_clock() - icount_get()) / SCALE_MS);
if (icount_align_option) {
g_string_append_printf(buf, "Max guest delay %"PRIi64" ms\n",
-max_delay / SCALE_MS);
g_string_append_printf(buf, "Max guest advance %"PRIi64" ms\n",
max_advance / SCALE_MS);
} else {
g_string_append_printf(buf, "Max guest delay NA\n");
g_string_append_printf(buf, "Max guest advance NA\n");
}
}
HumanReadableText *qmp_x_query_jit(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
if (!tcg_enabled()) {
error_setg(errp, "JIT information is only available with accel=tcg");
return NULL;
}
dump_exec_info(buf);
dump_drift_info(buf);
return human_readable_text_from_str(buf);
}
HumanReadableText *qmp_x_query_opcount(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
if (!tcg_enabled()) {
error_setg(errp,
"Opcode count information is only available with accel=tcg");
return NULL;
}
tcg_dump_op_count(buf);
return human_readable_text_from_str(buf);
}
#ifdef CONFIG_PROFILER
int64_t dev_time;
HumanReadableText *qmp_x_query_profile(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
static int64_t last_cpu_exec_time;
int64_t cpu_exec_time;
int64_t delta;
cpu_exec_time = tcg_cpu_exec_time();
delta = cpu_exec_time - last_cpu_exec_time;
g_string_append_printf(buf, "async time %" PRId64 " (%0.3f)\n",
dev_time, dev_time / (double)NANOSECONDS_PER_SECOND);
g_string_append_printf(buf, "qemu time %" PRId64 " (%0.3f)\n",
delta, delta / (double)NANOSECONDS_PER_SECOND);
last_cpu_exec_time = cpu_exec_time;
dev_time = 0;
return human_readable_text_from_str(buf);
}
#else
HumanReadableText *qmp_x_query_profile(Error **errp)
{
error_setg(errp, "Internal profiler not compiled");
return NULL;
}
#endif
static void hmp_tcg_register(void)
{
monitor_register_hmp_info_hrt("jit", qmp_x_query_jit);
monitor_register_hmp_info_hrt("opcount", qmp_x_query_opcount);
}
type_init(hmp_tcg_register);

17
accel/tcg/tcg-accel-ops.c
View File

@ -44,7 +44,18 @@
void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
{
uint32_t cflags = cpu->cluster_index << CF_CLUSTER_SHIFT;
uint32_t cflags;
/*
* Include the cluster number in the hash we use to look up TBs.
* This is important because a TB that is valid for one cluster at
* a given physical address and set of CPU flags is not necessarily
* valid for another:
* the two clusters may have different views of physical memory, or
* may have different CPU features (eg FPU present or absent).
*/
cflags = cpu->cluster_index << CF_CLUSTER_SHIFT;
cflags |= parallel ? CF_PARALLEL : 0;
cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
cpu->tcg_cflags = cflags;
@ -116,7 +127,7 @@ static inline int xlat_gdb_type(CPUState *cpu, int gdbtype)
return cputype;
}
static int tcg_insert_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len)
static int tcg_insert_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
{
CPUState *cpu;
int err = 0;
@ -147,7 +158,7 @@ static int tcg_insert_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len
}
}
static int tcg_remove_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len)
static int tcg_remove_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
{
CPUState *cpu;
int err = 0;

2
accel/tcg/tcg-all.c
View File

@ -25,7 +25,7 @@
#include "qemu/osdep.h"
#include "sysemu/tcg.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
#include "sysemu/cpu-timers.h"
#include "tcg/tcg.h"
#include "qapi/error.h"

1
accel/tcg/translate-all.c
View File

@ -49,7 +49,6 @@
#include "exec/translator.h"
#include "qemu/bitmap.h"
#include "qemu/qemu-print.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h"
#include "qemu/cacheinfo.h"
#include "exec/log.h"

2
accel/tcg/translator.c
View File

@ -16,7 +16,7 @@
#include "exec/log.h"
#include "exec/translator.h"
#include "exec/plugin-gen.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
/* Pairs with tcg_clear_temp_count.
To be called by #TranslatorOps.{translate_insn,tb_stop} if

2
accel/tcg/user-exec-stub.c
View File

@ -1,6 +1,6 @@
#include "qemu/osdep.h"
#include "hw/core/cpu.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
bool enable_cpu_pm = false;

12
accel/xen/xen-all.c
View File

@ -23,16 +23,6 @@
#include "migration/global_state.h"
#include "hw/boards.h"
//#define DEBUG_XEN
#ifdef DEBUG_XEN
#define DPRINTF(fmt, ...) \
do { fprintf(stderr, "xen: " fmt, ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
bool xen_allowed;
xc_interface *xen_xc;
@ -181,6 +171,8 @@ static int xen_init(MachineState *ms)
* opt out of system RAM being allocated by generic code
*/
mc->default_ram_id = NULL;
xen_mode = XEN_ATTACH;
return 0;
}

3
block/vvfat.c
View File

@ -2784,13 +2784,10 @@ static int handle_commits(BDRVVVFATState* s)
fail = -2;
break;
case ACTION_WRITEOUT: {
#ifndef NDEBUG
/* these variables are only used by assert() below */
direntry_t* entry = array_get(&(s->directory),
commit->param.writeout.dir_index);
uint32_t begin = begin_of_direntry(entry);
mapping_t* mapping = find_mapping_for_cluster(s, begin);
#endif
assert(mapping);
assert(mapping->begin == begin);

73
cpu.c
View File

@ -33,7 +33,7 @@
#endif
#include "sysemu/tcg.h"
#include "sysemu/kvm.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
#include "exec/translate-all.h"
@ -319,77 +319,6 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
}
#endif
/* Add a breakpoint. */
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
CPUBreakpoint **breakpoint)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUBreakpoint *bp;
if (cc->gdb_adjust_breakpoint) {
pc = cc->gdb_adjust_breakpoint(cpu, pc);
}
bp = g_malloc(sizeof(*bp));
bp->pc = pc;
bp->flags = flags;
/* keep all GDB-injected breakpoints in front */
if (flags & BP_GDB) {
QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
} else {
QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
}
if (breakpoint) {
*breakpoint = bp;
}
trace_breakpoint_insert(cpu->cpu_index, pc, flags);
return 0;
}
/* Remove a specific breakpoint. */
int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUBreakpoint *bp;
if (cc->gdb_adjust_breakpoint) {
pc = cc->gdb_adjust_breakpoint(cpu, pc);
}
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
if (bp->pc == pc && bp->flags == flags) {
cpu_breakpoint_remove_by_ref(cpu, bp);
return 0;
}
}
return -ENOENT;
}
/* Remove a specific breakpoint by reference. */
void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
{
QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
g_free(bp);
}
/* Remove all matching breakpoints. */
void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
{
CPUBreakpoint *bp, *next;
QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
if (bp->flags & mask) {
cpu_breakpoint_remove_by_ref(cpu, bp);
}
}
}
/* enable or disable single step mode. EXCP_DEBUG is returned by the
CPU loop after each instruction */
void cpu_single_step(CPUState *cpu, int enabled)

72
cpus-common.c
View File

@ -23,6 +23,7 @@
#include "hw/core/cpu.h"
#include "sysemu/cpus.h"
#include "qemu/lockable.h"
#include "trace/trace-root.h"
static QemuMutex qemu_cpu_list_lock;
static QemuCond exclusive_cond;
@ -368,3 +369,74 @@ void process_queued_cpu_work(CPUState *cpu)
qemu_mutex_unlock(&cpu->work_mutex);
qemu_cond_broadcast(&qemu_work_cond);
}
/* Add a breakpoint. */
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
CPUBreakpoint **breakpoint)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUBreakpoint *bp;
if (cc->gdb_adjust_breakpoint) {
pc = cc->gdb_adjust_breakpoint(cpu, pc);
}
bp = g_malloc(sizeof(*bp));
bp->pc = pc;
bp->flags = flags;
/* keep all GDB-injected breakpoints in front */
if (flags & BP_GDB) {
QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
} else {
QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
}
if (breakpoint) {
*breakpoint = bp;
}
trace_breakpoint_insert(cpu->cpu_index, pc, flags);
return 0;
}
/* Remove a specific breakpoint. */
int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUBreakpoint *bp;
if (cc->gdb_adjust_breakpoint) {
pc = cc->gdb_adjust_breakpoint(cpu, pc);
}
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
if (bp->pc == pc && bp->flags == flags) {
cpu_breakpoint_remove_by_ref(cpu, bp);
return 0;
}
}
return -ENOENT;
}
/* Remove a specific breakpoint by reference. */
void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
{
QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
g_free(bp);
}
/* Remove all matching breakpoints. */
void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
{
CPUBreakpoint *bp, *next;
QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
if (bp->flags & mask) {
cpu_breakpoint_remove_by_ref(cpu, bp);
}
}
}

76
docs/system/i386/xen.rst Normal file
View File

@ -0,0 +1,76 @@
Xen HVM guest support
=====================
Description
-----------
KVM has support for hosting Xen guests, intercepting Xen hypercalls and event
channel (Xen PV interrupt) delivery. This allows guests which expect to be
run under Xen to be hosted in QEMU under Linux/KVM instead.
Setup
-----
Xen mode is enabled by setting the ``xen-version`` property of the KVM
accelerator, for example for Xen 4.10:
.. parsed-literal::
|qemu_system| --accel kvm,xen-version=0x4000a
Additionally, virtual APIC support can be advertised to the guest through the
``xen-vapic`` CPU flag:
.. parsed-literal::
|qemu_system| --accel kvm,xen-version=0x4000a --cpu host,+xen_vapic
When Xen support is enabled, QEMU changes hypervisor identification (CPUID
0x40000000..0x4000000A) to Xen. The KVM identification and features are not
advertised to a Xen guest. If Hyper-V is also enabled, the Xen identification
moves to leaves 0x40000100..0x4000010A.
The Xen platform device is enabled automatically for a Xen guest. This allows
a guest to unplug all emulated devices, in order to use Xen PV block and network
drivers instead. Note that until the Xen PV device back ends are enabled to work
with Xen mode in QEMU, that is unlikely to cause significant joy. Linux guests
can be dissuaded from this by adding 'xen_emul_unplug=never' on their command
line, and it can also be noted that AHCI disk controllers are exempt from being
unplugged, as are passthrough VFIO PCI devices.
Properties
----------
The following properties exist on the KVM accelerator object:
``xen-version``
This property contains the Xen version in ``XENVER_version`` form, with the
major version in the top 16 bits and the minor version in the low 16 bits.
Setting this property enables the Xen guest support.
``xen-evtchn-max-pirq``
Xen PIRQs represent an emulated physical interrupt, either GSI or MSI, which
can be routed to an event channel instead of to the emulated I/O or local
APIC. By default, QEMU permits only 256 PIRQs because this allows maximum
compatibility with 32-bit MSI where the higher bits of the PIRQ# would need
to be in the upper 64 bits of the MSI message. For guests with large numbers
of PCI devices (and none which are limited to 32-bit addressing) it may be
desirable to increase this value.
``xen-gnttab-max-frames``
Xen grant tables are the means by which a Xen guest grants access to its
memory for PV back ends (disk, network, etc.). Since QEMU only supports v1
grant tables which are 8 bytes in size, each page (each frame) of the grant
table can reference 512 pages of guest memory. The default number of frames
is 64, allowing for 32768 pages of guest memory to be accessed by PV backends
through simultaneous grants. For guests with large numbers of PV devices and
high throughput, it may be desirable to increase this value.
OS requirements
---------------
The minimal Xen support in the KVM accelerator requires the host to be running
Linux v5.12 or newer. Later versions add optimisations: Linux v5.17 added
acceleration of interrupt delivery via the Xen PIRQ mechanism, and Linux v5.19
accelerated Xen PV timers and inter-processor interrupts (IPIs).

1
docs/system/target-i386.rst
View File

@ -27,6 +27,7 @@ Architectural features
i386/cpu
i386/hyperv
i386/xen
i386/kvm-pv
i386/sgx
i386/amd-memory-encryption

2
dump/dump-hmp-cmds.c
View File

@ -1,5 +1,5 @@
/*
* Human Monitor Interface commands
* Windows crashdump (Human Monitor Interface commands)
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.

35
dump/dump.c
View File

@ -14,25 +14,21 @@
#include "qemu/osdep.h"
#include "qemu/cutils.h"
#include "elf.h"
#include "exec/hwaddr.h"
#include "qemu/bswap.h"
#include "exec/target_page.h"
#include "monitor/monitor.h"
#include "sysemu/kvm.h"
#include "sysemu/dump.h"
#include "sysemu/memory_mapping.h"
#include "sysemu/runstate.h"
#include "sysemu/cpus.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-dump.h"
#include "qapi/qapi-events-dump.h"
#include "qapi/qmp/qerror.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#include "hw/misc/vmcoreinfo.h"
#include "migration/blocker.h"
#ifdef TARGET_X86_64
#include "hw/core/cpu.h"
#include "win_dump.h"
#endif
#include <zlib.h>
#ifdef CONFIG_LZO
@ -907,13 +903,13 @@ static void get_note_sizes(DumpState *s, const void *note,
if (dump_is_64bit(s)) {
const Elf64_Nhdr *hdr = note;
note_head_sz = sizeof(Elf64_Nhdr);
name_sz = tswap64(hdr->n_namesz);
desc_sz = tswap64(hdr->n_descsz);
name_sz = cpu_to_dump64(s, hdr->n_namesz);
desc_sz = cpu_to_dump64(s, hdr->n_descsz);
} else {
const Elf32_Nhdr *hdr = note;
note_head_sz = sizeof(Elf32_Nhdr);
name_sz = tswap32(hdr->n_namesz);
desc_sz = tswap32(hdr->n_descsz);
name_sz = cpu_to_dump32(s, hdr->n_namesz);
desc_sz = cpu_to_dump32(s, hdr->n_descsz);
}
if (note_head_size) {
@ -1860,7 +1856,7 @@ static void dump_init(DumpState *s, int fd, bool has_format,
}
if (!s->dump_info.page_size) {
s->dump_info.page_size = TARGET_PAGE_SIZE;
s->dump_info.page_size = qemu_target_page_size();
}
s->note_size = cpu_get_note_size(s->dump_info.d_class,
@ -2022,9 +2018,7 @@ static void dump_process(DumpState *s, Error **errp)
DumpQueryResult *result = NULL;
if (s->has_format && s->format == DUMP_GUEST_MEMORY_FORMAT_WIN_DMP) {
#ifdef TARGET_X86_64
create_win_dump(s, errp);
#endif
} else if (s->has_format && s->format != DUMP_GUEST_MEMORY_FORMAT_ELF) {
create_kdump_vmcore(s, errp);
} else {
@ -2127,12 +2121,10 @@ void qmp_dump_guest_memory(bool paging, const char *file,
}
#endif
#ifndef TARGET_X86_64
if (has_format && format == DUMP_GUEST_MEMORY_FORMAT_WIN_DMP) {
error_setg(errp, "Windows dump is only available for x86-64");
if (has_format && format == DUMP_GUEST_MEMORY_FORMAT_WIN_DMP
&& !win_dump_available(errp)) {
return;
}
#endif
#if !defined(WIN32)
if (strstart(file, "fd:", &p)) {
@ -2214,10 +2206,9 @@ DumpGuestMemoryCapability *qmp_query_dump_guest_memory_capability(Error **errp)
QAPI_LIST_APPEND(tail, DUMP_GUEST_MEMORY_FORMAT_KDUMP_SNAPPY);
#endif
/* Windows dump is available only if target is x86_64 */
#ifdef TARGET_X86_64
QAPI_LIST_APPEND(tail, DUMP_GUEST_MEMORY_FORMAT_WIN_DMP);
#endif
if (win_dump_available(NULL)) {
QAPI_LIST_APPEND(tail, DUMP_GUEST_MEMORY_FORMAT_WIN_DMP);
}
return cap;
}

6
dump/meson.build
View File

@ -1,4 +1,2 @@
softmmu_ss.add(files('dump-hmp-cmds.c'))
specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: [files('dump.c'), snappy, lzo])
specific_ss.add(when: ['CONFIG_SOFTMMU', 'TARGET_X86_64'], if_true: files('win_dump.c'))
softmmu_ss.add([files('dump.c', 'dump-hmp-cmds.c'), snappy, lzo])
specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: files('win_dump.c'))

38
dump/win_dump.c
View File

@ -1,5 +1,5 @@
/*
* Windows crashdump
* Windows crashdump (target specific implementations)
*
* Copyright (c) 2018 Virtuozzo International GmbH
*
@ -9,19 +9,21 @@
*/
#include "qemu/osdep.h"
#include "qemu/cutils.h"
#include "elf.h"
#include "exec/hwaddr.h"
#include "monitor/monitor.h"
#include "sysemu/kvm.h"
#include "sysemu/dump.h"
#include "sysemu/memory_mapping.h"
#include "sysemu/cpus.h"
#include "qapi/error.h"
#include "qapi/qmp/qerror.h"
#include "qemu/error-report.h"
#include "hw/misc/vmcoreinfo.h"
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
#include "qemu/win_dump_defs.h"
#include "win_dump.h"
#include "cpu.h"
#if defined(TARGET_X86_64)
bool win_dump_available(Error **errp)
{
return true;
}
static size_t win_dump_ptr_size(bool x64)
{
@ -475,3 +477,19 @@ out_cr3:
return;
}
#else /* !TARGET_X86_64 */
bool win_dump_available(Error **errp)
{
error_setg(errp, "Windows dump is only available for x86-64");
return false;
}
void create_win_dump(DumpState *s, Error **errp)
{
win_dump_available(errp);
}
#endif

5
dump/win_dump.h
View File

@ -11,7 +11,10 @@
#ifndef WIN_DUMP_H
#define WIN_DUMP_H
#include "qemu/win_dump_defs.h"
#include "sysemu/dump.h"
/* Check Windows dump availability for the current target */
bool win_dump_available(Error **errp);
void create_win_dump(DumpState *s, Error **errp);

3
gdbstub/gdbstub.c
View File

@ -48,8 +48,7 @@
#include "sysemu/runstate.h"
#include "semihosting/semihost.h"
#include "exec/exec-all.h"
#include "exec/hwaddr.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
#include "internals.h"

6
gdbstub/internals.h
View File

@ -9,9 +9,11 @@
#ifndef _INTERNALS_H_
#define _INTERNALS_H_
#include "exec/cpu-common.h"
bool gdb_supports_guest_debug(void);
int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len);
int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len);
int gdb_breakpoint_insert(CPUState *cs, int type, vaddr addr, vaddr len);
int gdb_breakpoint_remove(CPUState *cs, int type, vaddr addr, vaddr len);
void gdb_breakpoint_remove_all(CPUState *cs);
#endif /* _INTERNALS_H_ */

5
gdbstub/softmmu.c
View File

@ -11,7 +11,6 @@
#include "qemu/osdep.h"
#include "exec/gdbstub.h"
#include "exec/hwaddr.h"
#include "sysemu/cpus.h"
#include "internals.h"
@ -24,7 +23,7 @@ bool gdb_supports_guest_debug(void)
return false;
}
int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len)
int gdb_breakpoint_insert(CPUState *cs, int type, vaddr addr, vaddr len)
{
const AccelOpsClass *ops = cpus_get_accel();
if (ops->insert_breakpoint) {
@ -33,7 +32,7 @@ int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len)
return -ENOSYS;
}
int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len)
int gdb_breakpoint_remove(CPUState *cs, int type, vaddr addr, vaddr len)
{
const AccelOpsClass *ops = cpus_get_accel();
if (ops->remove_breakpoint) {

5
gdbstub/user.c
View File

@ -9,7 +9,6 @@
*/
#include "qemu/osdep.h"
#include "exec/hwaddr.h"
#include "exec/gdbstub.h"
#include "hw/core/cpu.h"
#include "internals.h"
@ -20,7 +19,7 @@ bool gdb_supports_guest_debug(void)
return true;
}
int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len)
int gdb_breakpoint_insert(CPUState *cs, int type, vaddr addr, vaddr len)
{
CPUState *cpu;
int err = 0;
@ -41,7 +40,7 @@ int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len)
}
}
int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len)
int gdb_breakpoint_remove(CPUState *cs, int type, vaddr addr, vaddr len)
{
CPUState *cpu;
int err = 0;

29
hmp-commands.hx
View File

@ -1815,3 +1815,32 @@ SRST
Dump the FDT in dtb format to *filename*.
ERST
#endif
#if defined(CONFIG_XEN_EMU)
{
.name = "xen-event-inject",
.args_type = "port:i",
.params = "port",
.help = "inject event channel",
.cmd = hmp_xen_event_inject,
},
SRST
``xen-event-inject`` *port*
Notify guest via event channel on port *port*.
ERST
{
.name = "xen-event-list",
.args_type = "",
.params = "",
.help = "list event channel state",
.cmd = hmp_xen_event_list,
},
SRST
``xen-event-list``
List event channels in the guest
ERST
#endif

1
hw/Kconfig
View File

@ -41,6 +41,7 @@ source tpm/Kconfig
source usb/Kconfig
source virtio/Kconfig
source vfio/Kconfig
source xen/Kconfig
source watchdog/Kconfig
# arch Kconfig

10
hw/acpi/ich9.c
View File

@ -36,7 +36,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9_tco.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
@ -291,9 +291,7 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
acpi_pm1_evt_power_down(&pm->acpi_regs);
}
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
bool smm_enabled,
qemu_irq sci_irq)
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq)
{
memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
memory_region_set_enabled(&pm->io, false);
@ -303,7 +301,7 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4,
pm->s4_val, !pm->smm_compat && !smm_enabled);
pm->s4_val, !pm->smm_compat && !pm->smm_enabled);
acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
@ -314,8 +312,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
"acpi-smi", 8);
memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
pm->smm_enabled = smm_enabled;
if (pm->enable_tco) {
acpi_pm_tco_init(&pm->tco_regs, &pm->io);
}

2
hw/acpi/ich9_tco.c
View File

@ -9,7 +9,7 @@
#include "qemu/osdep.h"
#include "sysemu/watchdog.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
#include "migration/vmstate.h"
#include "hw/acpi/ich9_tco.h"

2
hw/arm/sbsa-ref.c
View File

@ -554,7 +554,7 @@ static void create_ahci(const SBSAMachineState *sms)
if (hd[i] == NULL) {
continue;
}
ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
}
}

45
hw/audio/ac97.c
View File

@ -26,43 +26,7 @@
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "qom/object.h"
enum {
AC97_Reset = 0x00,
AC97_Master_Volume_Mute = 0x02,
AC97_Headphone_Volume_Mute = 0x04,
AC97_Master_Volume_Mono_Mute = 0x06,
AC97_Master_Tone_RL = 0x08,
AC97_PC_BEEP_Volume_Mute = 0x0A,
AC97_Phone_Volume_Mute = 0x0C,
AC97_Mic_Volume_Mute = 0x0E,
AC97_Line_In_Volume_Mute = 0x10,
AC97_CD_Volume_Mute = 0x12,
AC97_Video_Volume_Mute = 0x14,
AC97_Aux_Volume_Mute = 0x16,
AC97_PCM_Out_Volume_Mute = 0x18,
AC97_Record_Select = 0x1A,
AC97_Record_Gain_Mute = 0x1C,
AC97_Record_Gain_Mic_Mute = 0x1E,
AC97_General_Purpose = 0x20,
AC97_3D_Control = 0x22,
AC97_AC_97_RESERVED = 0x24,
AC97_Powerdown_Ctrl_Stat = 0x26,
AC97_Extended_Audio_ID = 0x28,
AC97_Extended_Audio_Ctrl_Stat = 0x2A,
AC97_PCM_Front_DAC_Rate = 0x2C,
AC97_PCM_Surround_DAC_Rate = 0x2E,
AC97_PCM_LFE_DAC_Rate = 0x30,
AC97_PCM_LR_ADC_Rate = 0x32,
AC97_MIC_ADC_Rate = 0x34,
AC97_6Ch_Vol_C_LFE_Mute = 0x36,
AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
AC97_Vendor_Reserved = 0x58,
AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */
AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */
AC97_Vendor_ID1 = 0x7c,
AC97_Vendor_ID2 = 0x7e
};
#include "ac97.h"
#define SOFT_VOLUME
#define SR_FIFOE 16 /* rwc */
@ -121,11 +85,6 @@ enum {
#define BD_IOC (1 << 31)
#define BD_BUP (1 << 30)
#define EACS_VRA 1
#define EACS_VRM 8
#define MUTE_SHIFT 15
#define TYPE_AC97 "AC97"
OBJECT_DECLARE_SIMPLE_TYPE(AC97LinkState, AC97)
@ -1295,7 +1254,7 @@ static const MemoryRegionOps ac97_io_nabm_ops = {
static void ac97_on_reset(DeviceState *dev)
{
AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev);
AC97LinkState *s = AC97(dev);
reset_bm_regs(s, &s->bm_regs[0]);
reset_bm_regs(s, &s->bm_regs[1]);

65
hw/audio/ac97.h Normal file
View File

@ -0,0 +1,65 @@
/*
* Copyright (C) 2006 InnoTek Systemberatung GmbH
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* you can redistribute it and/or modify it under the terms of the GNU
* General Public License as published by the Free Software Foundation,
* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
* distribution. VirtualBox OSE is distributed in the hope that it will
* be useful, but WITHOUT ANY WARRANTY of any kind.
*
* If you received this file as part of a commercial VirtualBox
* distribution, then only the terms of your commercial VirtualBox
* license agreement apply instead of the previous paragraph.
*
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
#ifndef AC97_H
#define AC97_H
enum {
AC97_Reset = 0x00,
AC97_Master_Volume_Mute = 0x02,
AC97_Headphone_Volume_Mute = 0x04,
AC97_Master_Volume_Mono_Mute = 0x06,
AC97_Master_Tone_RL = 0x08,
AC97_PC_BEEP_Volume_Mute = 0x0A,
AC97_Phone_Volume_Mute = 0x0C,
AC97_Mic_Volume_Mute = 0x0E,
AC97_Line_In_Volume_Mute = 0x10,
AC97_CD_Volume_Mute = 0x12,
AC97_Video_Volume_Mute = 0x14,
AC97_Aux_Volume_Mute = 0x16,
AC97_PCM_Out_Volume_Mute = 0x18,
AC97_Record_Select = 0x1A,
AC97_Record_Gain_Mute = 0x1C,
AC97_Record_Gain_Mic_Mute = 0x1E,
AC97_General_Purpose = 0x20,
AC97_3D_Control = 0x22,
AC97_AC_97_RESERVED = 0x24,
AC97_Powerdown_Ctrl_Stat = 0x26,
AC97_Extended_Audio_ID = 0x28,
AC97_Extended_Audio_Ctrl_Stat = 0x2A,
AC97_PCM_Front_DAC_Rate = 0x2C,
AC97_PCM_Surround_DAC_Rate = 0x2E,
AC97_PCM_LFE_DAC_Rate = 0x30,
AC97_PCM_LR_ADC_Rate = 0x32,
AC97_MIC_ADC_Rate = 0x34,
AC97_6Ch_Vol_C_LFE_Mute = 0x36,
AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
AC97_Vendor_Reserved = 0x58,
AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */
AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */
AC97_Vendor_ID1 = 0x7c,
AC97_Vendor_ID2 = 0x7e
};
#define EACS_VRA 1
#define EACS_VRM 8
#define MUTE_SHIFT 15
#endif /* AC97_H */

5
hw/audio/cs4231a.c
View File

@ -668,16 +668,17 @@ static void cs4231a_initfn (Object *obj)
static void cs4231a_realizefn (DeviceState *dev, Error **errp)
{
ISADevice *d = ISA_DEVICE (dev);
ISABus *bus = isa_bus_from_device(d);
CSState *s = CS4231A (dev);
IsaDmaClass *k;
s->isa_dma = isa_get_dma(isa_bus_from_device(d), s->dma);
s->isa_dma = isa_bus_get_dma(bus, s->dma);
if (!s->isa_dma) {
error_setg(errp, "ISA controller does not support DMA");
return;
}
s->pic = isa_get_irq(d, s->irq);
s->pic = isa_bus_get_irq(bus, s->irq);
k = ISADMA_GET_CLASS(s->isa_dma);
k->register_channel(s->isa_dma, s->dma, cs_dma_read, s);

10
hw/audio/es1370.c
View File

@ -256,6 +256,9 @@ static void print_sctl (uint32_t val)
#define lwarn(...)
#endif
#define TYPE_ES1370 "ES1370"
OBJECT_DECLARE_SIMPLE_TYPE(ES1370State, ES1370)
struct chan {
uint32_t shift;
uint32_t leftover;
@ -278,7 +281,6 @@ struct ES1370State {
uint32_t codec;
uint32_t sctl;
};
typedef struct ES1370State ES1370State;
struct chan_bits {
uint32_t ctl_en;
@ -292,9 +294,6 @@ struct chan_bits {
uint32_t *old_freq, uint32_t *new_freq);
};
#define TYPE_ES1370 "ES1370"
OBJECT_DECLARE_SIMPLE_TYPE(ES1370State, ES1370)
static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
uint32_t *old_freq, uint32_t *new_freq);
static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
@ -844,7 +843,8 @@ static const VMStateDescription vmstate_es1370 = {
static void es1370_on_reset(DeviceState *dev)
{
ES1370State *s = container_of(dev, ES1370State, dev.qdev);
ES1370State *s = ES1370(dev);
es1370_reset (s);
}

5
hw/audio/gus.c
View File

@ -236,11 +236,12 @@ static const MemoryRegionPortio gus_portio_list2[] = {
static void gus_realizefn (DeviceState *dev, Error **errp)
{
ISADevice *d = ISA_DEVICE(dev);
ISABus *bus = isa_bus_from_device(d);
GUSState *s = GUS (dev);
IsaDmaClass *k;
struct audsettings as;
s->isa_dma = isa_get_dma(isa_bus_from_device(d), s->emu.gusdma);
s->isa_dma = isa_bus_get_dma(bus, s->emu.gusdma);
if (!s->isa_dma) {
error_setg(errp, "ISA controller does not support DMA");
return;
@ -282,7 +283,7 @@ static void gus_realizefn (DeviceState *dev, Error **errp)
s->emu.himemaddr = s->himem;
s->emu.gusdatapos = s->emu.himemaddr + 1024 * 1024 + 32;
s->emu.opaque = s;
s->pic = isa_get_irq(d, s->emu.gusirq);
s->pic = isa_bus_get_irq(bus, s->emu.gusirq);
AUD_set_active_out (s->voice, 1);
}

7
hw/audio/hda-codec.c
View File

@ -145,7 +145,9 @@ static const char *fmt2name[] = {
[ AUDIO_FORMAT_S32 ] = "PCM-S32",
};
typedef struct HDAAudioState HDAAudioState;
#define TYPE_HDA_AUDIO "hda-audio"
OBJECT_DECLARE_SIMPLE_TYPE(HDAAudioState, HDA_AUDIO)
typedef struct HDAAudioStream HDAAudioStream;
struct HDAAudioStream {
@ -171,9 +173,6 @@ struct HDAAudioStream {
int64_t buft_start;
};
#define TYPE_HDA_AUDIO "hda-audio"
OBJECT_DECLARE_SIMPLE_TYPE(HDAAudioState, HDA_AUDIO)
struct HDAAudioState {
HDACodecDevice hda;
const char *name;

7
hw/audio/sb16.c
View File

@ -1398,17 +1398,18 @@ static void sb16_initfn (Object *obj)
static void sb16_realizefn (DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE (dev);
ISABus *bus = isa_bus_from_device(isadev);
SB16State *s = SB16 (dev);
IsaDmaClass *k;
s->isa_hdma = isa_get_dma(isa_bus_from_device(isadev), s->hdma);
s->isa_dma = isa_get_dma(isa_bus_from_device(isadev), s->dma);
s->isa_hdma = isa_bus_get_dma(bus, s->hdma);
s->isa_dma = isa_bus_get_dma(bus, s->dma);
if (!s->isa_dma || !s->isa_hdma) {
error_setg(errp, "ISA controller does not support DMA");
return;
}
s->pic = isa_get_irq(isadev, s->irq);
s->pic = isa_bus_get_irq(bus, s->irq);
s->mixer_regs[0x80] = magic_of_irq (s->irq);
s->mixer_regs[0x81] = (1 << s->dma) | (1 << s->hdma);

5
hw/block/fdc-isa.c
View File

@ -86,6 +86,7 @@ static const MemoryRegionPortio fdc_portio_list[] = {
static void isabus_fdc_realize(DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE(dev);
ISABus *bus = isa_bus_from_device(isadev);
FDCtrlISABus *isa = ISA_FDC(dev);
FDCtrl *fdctrl = &isa->state;
Error *err = NULL;
@ -94,11 +95,11 @@ static void isabus_fdc_realize(DeviceState *dev, Error **errp)
isa->iobase, fdc_portio_list, fdctrl,
"fdc");
fdctrl->irq = isa_get_irq(isadev, isa->irq);
fdctrl->irq = isa_bus_get_irq(bus, isa->irq);
fdctrl->dma_chann = isa->dma;
if (fdctrl->dma_chann != -1) {
IsaDmaClass *k;
fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
fdctrl->dma = isa_bus_get_dma(bus, isa->dma);
if (!fdctrl->dma) {
error_setg(errp, "ISA controller does not support DMA");
return;

2
hw/core/ptimer.c
View File

@ -10,7 +10,7 @@
#include "hw/ptimer.h"
#include "migration/vmstate.h"
#include "qemu/host-utils.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/qtest.h"
#include "block/aio.h"

2
hw/core/qdev.c
View File

@ -330,7 +330,7 @@ bool qdev_machine_modified(void)
return qdev_hot_added || qdev_hot_removed;
}
BusState *qdev_get_parent_bus(DeviceState *dev)
BusState *qdev_get_parent_bus(const DeviceState *dev)
{
return dev->parent_bus;
}

127
hw/display/sm501.c
View File

@ -28,6 +28,7 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/char/serial.h"
#include "ui/console.h"
#include "hw/sysbus.h"
@ -691,7 +692,7 @@ static void sm501_2d_operation(SM501State *s)
unsigned int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF;
int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt);
bool overlap = false;
bool overlap = false, fallback = false;
if ((s->twoD_stretch >> 16) & 0xF) {
qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n");
@ -753,7 +754,7 @@ static void sm501_2d_operation(SM501State *s)
}
if ((rop_mode && rop == 0x5) || (!rop_mode && rop == 0x55)) {
/* Invert dest, is there a way to do this with pixman? */
/* DSTINVERT, is there a way to do this with pixman? */
unsigned int x, y, i;
uint8_t *d = s->local_mem + dst_base;
@ -763,6 +764,34 @@ static void sm501_2d_operation(SM501State *s)
stn_he_p(&d[i], bypp, ~ldn_he_p(&d[i], bypp));
}
}
} else if (!rop_mode && rop == 0x99) {
/* DSxn, is there a way to do this with pixman? */
unsigned int x, y, i, j;
uint8_t *sp = s->local_mem + src_base;
uint8_t *d = s->local_mem + dst_base;
for (y = 0; y < height; y++) {
i = (dst_x + (dst_y + y) * dst_pitch) * bypp;
j = (src_x + (src_y + y) * src_pitch) * bypp;
for (x = 0; x < width; x++, i += bypp, j += bypp) {
stn_he_p(&d[i], bypp,
~(ldn_he_p(&sp[j], bypp) ^ ldn_he_p(&d[i], bypp)));
}
}
} else if (!rop_mode && rop == 0xee) {
/* SRCPAINT, is there a way to do this with pixman? */
unsigned int x, y, i, j;
uint8_t *sp = s->local_mem + src_base;
uint8_t *d = s->local_mem + dst_base;
for (y = 0; y < height; y++) {
i = (dst_x + (dst_y + y) * dst_pitch) * bypp;
j = (src_x + (src_y + y) * src_pitch) * bypp;
for (x = 0; x < width; x++, i += bypp, j += bypp) {
stn_he_p(&d[i], bypp,
ldn_he_p(&sp[j], bypp) | ldn_he_p(&d[i], bypp));
}
}
} else {
/* Do copy src for unimplemented ops, better than unpainted area */
if ((rop_mode && (rop != 0xc || rop2_source_is_pattern)) ||
@ -806,25 +835,48 @@ static void sm501_2d_operation(SM501State *s)
if (tmp_stride * sizeof(uint32_t) * height > sizeof(tmp_buf)) {
tmp = g_malloc(tmp_stride * sizeof(uint32_t) * height);
}
pixman_blt((uint32_t *)&s->local_mem[src_base], tmp,
src_pitch * bypp / sizeof(uint32_t),
tmp_stride, 8 * bypp, 8 * bypp,
src_x, src_y, 0, 0, width, height);
pixman_blt(tmp, (uint32_t *)&s->local_mem[dst_base],
tmp_stride,
dst_pitch * bypp / sizeof(uint32_t),
8 * bypp, 8 * bypp,
0, 0, dst_x, dst_y, width, height);
fallback = !pixman_blt((uint32_t *)&s->local_mem[src_base],
tmp,
src_pitch * bypp / sizeof(uint32_t),
tmp_stride,
8 * bypp, 8 * bypp,
src_x, src_y, 0, 0, width, height);
if (!fallback) {
fallback = !pixman_blt(tmp,
(uint32_t *)&s->local_mem[dst_base],
tmp_stride,
dst_pitch * bypp / sizeof(uint32_t),
8 * bypp, 8 * bypp,
0, 0, dst_x, dst_y, width, height);
}
if (tmp != tmp_buf) {
g_free(tmp);
}
} else {
pixman_blt((uint32_t *)&s->local_mem[src_base],
(uint32_t *)&s->local_mem[dst_base],
src_pitch * bypp / sizeof(uint32_t),
dst_pitch * bypp / sizeof(uint32_t),
8 * bypp, 8 * bypp,
src_x, src_y, dst_x, dst_y, width, height);
fallback = !pixman_blt((uint32_t *)&s->local_mem[src_base],
(uint32_t *)&s->local_mem[dst_base],
src_pitch * bypp / sizeof(uint32_t),
dst_pitch * bypp / sizeof(uint32_t),
8 * bypp, 8 * bypp, src_x, src_y,
dst_x, dst_y, width, height);
}
if (fallback) {
uint8_t *sp = s->local_mem + src_base;
uint8_t *d = s->local_mem + dst_base;
unsigned int y, i, j;
for (y = 0; y < height; y++) {
if (overlap) { /* overlap also means rtl */
i = (dst_y + height - 1 - y) * dst_pitch;
i = (dst_x + i) * bypp;
j = (src_y + height - 1 - y) * src_pitch;
j = (src_x + j) * bypp;
memmove(&d[i], &sp[j], width * bypp);
} else {
i = (dst_x + (dst_y + y) * dst_pitch) * bypp;
j = (src_x + (src_y + y) * src_pitch) * bypp;
memcpy(&d[i], &sp[j], width * bypp);
}
}
}
}
break;
@ -839,13 +891,19 @@ static void sm501_2d_operation(SM501State *s)
color = cpu_to_le16(color);
}
if (width == 1 && height == 1) {
unsigned int i = (dst_x + dst_y * dst_pitch) * bypp;
stn_he_p(&s->local_mem[dst_base + i], bypp, color);
} else {
pixman_fill((uint32_t *)&s->local_mem[dst_base],
dst_pitch * bypp / sizeof(uint32_t),
8 * bypp, dst_x, dst_y, width, height, color);
if ((width == 1 && height == 1) ||
!pixman_fill((uint32_t *)&s->local_mem[dst_base],
dst_pitch * bypp / sizeof(uint32_t), 8 * bypp,
dst_x, dst_y, width, height, color)) {
/* fallback when pixman failed or we don't want to call it */
uint8_t *d = s->local_mem + dst_base;
unsigned int x, y, i;
for (y = 0; y < height; y++, i += dst_pitch * bypp) {
i = (dst_x + (dst_y + y) * dst_pitch) * bypp;
for (x = 0; x < width; x++, i += bypp) {
stn_he_p(&d[i], bypp, color);
}
}
}
break;
}
@ -1943,15 +2001,14 @@ struct SM501SysBusState {
/*< public >*/
SM501State state;
uint32_t vram_size;
uint32_t base;
SerialMM serial;
OHCISysBusState ohci;
};
static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
{
SM501SysBusState *s = SYSBUS_SM501(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
DeviceState *usb_dev;
MemoryRegion *mr;
sm501_init(&s->state, dev, s->vram_size);
@ -1964,13 +2021,10 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->state.mmio_region);
/* bridge to usb host emulation module */
usb_dev = qdev_new("sysbus-ohci");
qdev_prop_set_uint32(usb_dev, "num-ports", 2);
qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->ohci), &error_fatal);
memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ohci), 0));
sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->ohci));
/* bridge to serial emulation module */
sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal);
@ -1981,7 +2035,6 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
static Property sm501_sysbus_properties[] = {
DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0),
DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0),
DEFINE_PROP_END_OF_LIST(),
};
@ -2017,15 +2070,19 @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
static void sm501_sysbus_init(Object *o)
{
SM501SysBusState *sm501 = SYSBUS_SM501(o);
OHCISysBusState *ohci = &sm501->ohci;
SerialMM *smm = &sm501->serial;
object_initialize_child(o, "ohci", ohci, TYPE_SYSBUS_OHCI);
object_property_add_alias(o, "dma-offset", OBJECT(ohci), "dma-offset");
qdev_prop_set_uint32(DEVICE(ohci), "num-ports", 2);
object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM);
qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2);
qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
object_property_add_alias(o, "chardev",
OBJECT(smm), "chardev");
object_property_add_alias(o, "chardev", OBJECT(smm), "chardev");
}
static const TypeInfo sm501_sysbus_info = {

2
hw/dma/i82374.c
View File

@ -125,7 +125,7 @@ static void i82374_realize(DeviceState *dev, Error **errp)
I82374State *s = I82374(dev);
ISABus *isa_bus = isa_bus_from_device(ISA_DEVICE(dev));
if (isa_get_dma(isa_bus, 0)) {
if (isa_bus_get_dma(isa_bus, 0)) {
error_setg(errp, "DMA already initialized on ISA bus");
return;
}

2
hw/hppa/machine.c
View File

@ -98,7 +98,7 @@ static ISABus *hppa_isa_bus(void)
isa_irqs = i8259_init(isa_bus,
/* qemu_allocate_irq(dino_set_isa_irq, s, 0)); */
NULL);
isa_bus_irqs(isa_bus, isa_irqs);
isa_bus_register_input_irqs(isa_bus, isa_irqs);
return isa_bus;
}

39
hw/i2c/smbus_ich9.c
View File

@ -27,7 +27,7 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
#include "qom/object.h"
#include "hw/acpi/acpi_aml_interface.h"
@ -80,6 +80,18 @@ static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
}
}
static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
{
ICH9SMBState *s = pmsmb->opaque;
if (enabled == s->irq_enabled) {
return;
}
s->irq_enabled = enabled;
pci_set_irq(&s->dev, enabled);
}
static void ich9_smbus_realize(PCIDevice *d, Error **errp)
{
ICH9SMBState *s = ICH9_SMB_DEVICE(d);
@ -93,6 +105,9 @@ static void ich9_smbus_realize(PCIDevice *d, Error **errp)
pm_smbus_init(&d->qdev, &s->smb, false);
pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
&s->smb.io);
s->smb.set_irq = ich9_smb_set_irq;
s->smb.opaque = s;
}
static void build_ich9_smb_aml(AcpiDevAmlIf *adev, Aml *scope)
@ -125,28 +140,6 @@ static void ich9_smb_class_init(ObjectClass *klass, void *data)
adevc->build_dev_aml = build_ich9_smb_aml;
}
static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
{
ICH9SMBState *s = pmsmb->opaque;
if (enabled == s->irq_enabled) {
return;
}
s->irq_enabled = enabled;
pci_set_irq(&s->dev, enabled);
}
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
{
PCIDevice *d =
pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
ICH9SMBState *s = ICH9_SMB_DEVICE(d);
s->smb.set_irq = ich9_smb_set_irq;
s->smb.opaque = s;
return s->smb.smbus;
}
static const TypeInfo ich9_smb_info = {
.name = TYPE_ICH9_SMB_DEVICE,
.parent = TYPE_PCI_DEVICE,

5
hw/i386/Kconfig
View File

@ -136,3 +136,8 @@ config VMPORT
config VMMOUSE
bool
depends on VMPORT
config XEN_EMU
bool
default y
depends on KVM && (I386 || X86_64)

3
hw/i386/acpi-build.c
View File

@ -55,10 +55,11 @@
#include "hw/hyperv/vmbus-bridge.h"
/* Supported chipsets: */
#include "hw/southbridge/ich9.h"
#include "hw/southbridge/piix.h"
#include "hw/acpi/pcihp.h"
#include "hw/i386/fw_cfg.h"
#include "hw/i386/ich9.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-host/i440fx.h"
#include "hw/pci-host/q35.h"

3
hw/i386/kvm/ioapic.c
View File

@ -12,9 +12,8 @@
#include "qemu/osdep.h"
#include "monitor/monitor.h"
#include "hw/i386/x86.h"
#include "hw/qdev-properties.h"
#include "hw/i386/ioapic_internal.h"
#include "hw/intc/ioapic_internal.h"
#include "hw/intc/kvm_irqcount.h"
#include "sysemu/kvm.h"

13
hw/i386/kvm/meson.build
View File

@ -4,5 +4,18 @@ i386_kvm_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c'))
i386_kvm_ss.add(when: 'CONFIG_I8254', if_true: files('i8254.c'))
i386_kvm_ss.add(when: 'CONFIG_I8259', if_true: files('i8259.c'))
i386_kvm_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
i386_kvm_ss.add(when: 'CONFIG_XEN_EMU', if_true: files(
'xen_overlay.c',
'xen_evtchn.c',
'xen_gnttab.c',
'xen_xenstore.c',
))
i386_ss.add_all(when: 'CONFIG_KVM', if_true: i386_kvm_ss)
xen_stubs_ss = ss.source_set()
xen_stubs_ss.add(when: 'CONFIG_XEN_EMU', if_false: files(
'xen-stubs.c',
))
specific_ss.add_all(when: 'CONFIG_SOFTMMU', if_true: xen_stubs_ss)

5
hw/i386/kvm/trace-events Normal file
View File

@ -0,0 +1,5 @@
kvm_xen_map_pirq(int pirq, int gsi) "pirq %d gsi %d"
kvm_xen_unmap_pirq(int pirq, int gsi) "pirq %d gsi %d"
kvm_xen_get_free_pirq(int pirq, int type) "pirq %d type %d"
kvm_xen_bind_pirq(int pirq, int port) "pirq %d port %d"
kvm_xen_unmask_pirq(int pirq, char *dev, int vector) "pirq %d dev %s vector %d"

1
hw/i386/kvm/trace.h Normal file
View File

@ -0,0 +1 @@
#include "trace/trace-hw_i386_kvm.h"

44
hw/i386/kvm/xen-stubs.c Normal file
View File

@ -0,0 +1,44 @@
/*
* QEMU Xen emulation: QMP stubs
*
* Copyright © 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Authors: David Woodhouse <dwmw2@infradead.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-misc-target.h"
#include "xen_evtchn.h"
void xen_evtchn_snoop_msi(PCIDevice *dev, bool is_msix, unsigned int vector,
uint64_t addr, uint32_t data, bool is_masked)
{
}
void xen_evtchn_remove_pci_device(PCIDevice *dev)
{
}
bool xen_evtchn_deliver_pirq_msi(uint64_t address, uint32_t data)
{
return false;
}
#ifdef TARGET_I386
EvtchnInfoList *qmp_xen_event_list(Error **errp)
{
error_setg(errp, "Xen event channel emulation not enabled");
return NULL;
}
void qmp_xen_event_inject(uint32_t port, Error **errp)
{
error_setg(errp, "Xen event channel emulation not enabled");
}
#endif

2341
hw/i386/kvm/xen_evtchn.c Normal file
View File

File diff suppressed because it is too large Load Diff

88
hw/i386/kvm/xen_evtchn.h Normal file
View File

@ -0,0 +1,88 @@
/*
* QEMU Xen emulation: Event channel support
*
* Copyright © 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Authors: David Woodhouse <dwmw2@infradead.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef QEMU_XEN_EVTCHN_H
#define QEMU_XEN_EVTCHN_H
#include "hw/sysbus.h"
typedef uint32_t evtchn_port_t;
void xen_evtchn_create(void);
int xen_evtchn_soft_reset(void);
int xen_evtchn_set_callback_param(uint64_t param);
void xen_evtchn_connect_gsis(qemu_irq *system_gsis);
void xen_evtchn_set_callback_level(int level);
int xen_evtchn_set_port(uint16_t port);
bool xen_evtchn_set_gsi(int gsi, int level);
void xen_evtchn_snoop_msi(PCIDevice *dev, bool is_msix, unsigned int vector,
uint64_t addr, uint32_t data, bool is_masked);
void xen_evtchn_remove_pci_device(PCIDevice *dev);
struct kvm_irq_routing_entry;
int xen_evtchn_translate_pirq_msi(struct kvm_irq_routing_entry *route,
uint64_t address, uint32_t data);
bool xen_evtchn_deliver_pirq_msi(uint64_t address, uint32_t data);
/*
* These functions mirror the libxenevtchn library API, providing the QEMU
* backend side of "interdomain" event channels.
*/
struct xenevtchn_handle;
struct xenevtchn_handle *xen_be_evtchn_open(void);
int xen_be_evtchn_bind_interdomain(struct xenevtchn_handle *xc, uint32_t domid,
evtchn_port_t guest_port);
int xen_be_evtchn_unbind(struct xenevtchn_handle *xc, evtchn_port_t port);
int xen_be_evtchn_close(struct xenevtchn_handle *xc);
int xen_be_evtchn_fd(struct xenevtchn_handle *xc);
int xen_be_evtchn_notify(struct xenevtchn_handle *xc, evtchn_port_t port);
int xen_be_evtchn_unmask(struct xenevtchn_handle *xc, evtchn_port_t port);
int xen_be_evtchn_pending(struct xenevtchn_handle *xc);
/* Apart from this which is a local addition */
int xen_be_evtchn_get_guest_port(struct xenevtchn_handle *xc);
struct evtchn_status;
struct evtchn_close;
struct evtchn_unmask;
struct evtchn_bind_virq;
struct evtchn_bind_pirq;
struct evtchn_bind_ipi;
struct evtchn_send;
struct evtchn_alloc_unbound;
struct evtchn_bind_interdomain;
struct evtchn_bind_vcpu;
struct evtchn_reset;
int xen_evtchn_status_op(struct evtchn_status *status);
int xen_evtchn_close_op(struct evtchn_close *close);
int xen_evtchn_unmask_op(struct evtchn_unmask *unmask);
int xen_evtchn_bind_virq_op(struct evtchn_bind_virq *virq);
int xen_evtchn_bind_pirq_op(struct evtchn_bind_pirq *pirq);
int xen_evtchn_bind_ipi_op(struct evtchn_bind_ipi *ipi);
int xen_evtchn_send_op(struct evtchn_send *send);
int xen_evtchn_alloc_unbound_op(struct evtchn_alloc_unbound *alloc);
int xen_evtchn_bind_interdomain_op(struct evtchn_bind_interdomain *interdomain);
int xen_evtchn_bind_vcpu_op(struct evtchn_bind_vcpu *vcpu);
int xen_evtchn_reset_op(struct evtchn_reset *reset);
struct physdev_map_pirq;
struct physdev_unmap_pirq;
struct physdev_eoi;
struct physdev_irq_status_query;
struct physdev_get_free_pirq;
int xen_physdev_map_pirq(struct physdev_map_pirq *map);
int xen_physdev_unmap_pirq(struct physdev_unmap_pirq *unmap);
int xen_physdev_eoi_pirq(struct physdev_eoi *eoi);
int xen_physdev_query_pirq(struct physdev_irq_status_query *query);
int xen_physdev_get_free_pirq(struct physdev_get_free_pirq *get);
#endif /* QEMU_XEN_EVTCHN_H */

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/*
* QEMU Xen emulation: Grant table support
*
* Copyright © 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Authors: David Woodhouse <dwmw2@infradead.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
#include "qemu/module.h"
#include "qemu/lockable.h"
#include "qemu/main-loop.h"
#include "qapi/error.h"
#include "qom/object.h"
#include "exec/target_page.h"
#include "exec/address-spaces.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/xen/xen.h"
#include "xen_overlay.h"
#include "xen_gnttab.h"
#include "sysemu/kvm.h"
#include "sysemu/kvm_xen.h"
#include "hw/xen/interface/memory.h"
#include "hw/xen/interface/grant_table.h"
#define TYPE_XEN_GNTTAB "xen-gnttab"
OBJECT_DECLARE_SIMPLE_TYPE(XenGnttabState, XEN_GNTTAB)
#define XEN_PAGE_SHIFT 12
#define XEN_PAGE_SIZE (1ULL << XEN_PAGE_SHIFT)
#define ENTRIES_PER_FRAME_V1 (XEN_PAGE_SIZE / sizeof(grant_entry_v1_t))
struct XenGnttabState {
/*< private >*/
SysBusDevice busdev;
/*< public >*/
QemuMutex gnt_lock;
uint32_t nr_frames;
uint32_t max_frames;
union {
grant_entry_v1_t *v1;
/* Theoretically, v2 support could be added here. */
} entries;
MemoryRegion gnt_frames;
MemoryRegion *gnt_aliases;
uint64_t *gnt_frame_gpas;
};
struct XenGnttabState *xen_gnttab_singleton;
static void xen_gnttab_realize(DeviceState *dev, Error **errp)
{
XenGnttabState *s = XEN_GNTTAB(dev);
int i;
if (xen_mode != XEN_EMULATE) {
error_setg(errp, "Xen grant table support is for Xen emulation");
return;
}
s->nr_frames = 0;
s->max_frames = kvm_xen_get_gnttab_max_frames();
memory_region_init_ram(&s->gnt_frames, OBJECT(dev), "xen:grant_table",
XEN_PAGE_SIZE * s->max_frames, &error_abort);
memory_region_set_enabled(&s->gnt_frames, true);
s->entries.v1 = memory_region_get_ram_ptr(&s->gnt_frames);
memset(s->entries.v1, 0, XEN_PAGE_SIZE * s->max_frames);
/* Create individual page-sizes aliases for overlays */
s->gnt_aliases = (void *)g_new0(MemoryRegion, s->max_frames);
s->gnt_frame_gpas = (void *)g_new(uint64_t, s->max_frames);
for (i = 0; i < s->max_frames; i++) {
memory_region_init_alias(&s->gnt_aliases[i], OBJECT(dev),
NULL, &s->gnt_frames,
i * XEN_PAGE_SIZE, XEN_PAGE_SIZE);
s->gnt_frame_gpas[i] = INVALID_GPA;
}
qemu_mutex_init(&s->gnt_lock);
xen_gnttab_singleton = s;
}
static int xen_gnttab_post_load(void *opaque, int version_id)
{
XenGnttabState *s = XEN_GNTTAB(opaque);
uint32_t i;
for (i = 0; i < s->nr_frames; i++) {
if (s->gnt_frame_gpas[i] != INVALID_GPA) {
xen_overlay_do_map_page(&s->gnt_aliases[i], s->gnt_frame_gpas[i]);
}
}
return 0;
}
static bool xen_gnttab_is_needed(void *opaque)
{
return xen_mode == XEN_EMULATE;
}
static const VMStateDescription xen_gnttab_vmstate = {
.name = "xen_gnttab",
.version_id = 1,
.minimum_version_id = 1,
.needed = xen_gnttab_is_needed,
.post_load = xen_gnttab_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32(nr_frames, XenGnttabState),
VMSTATE_VARRAY_UINT32(gnt_frame_gpas, XenGnttabState, nr_frames, 0,
vmstate_info_uint64, uint64_t),
VMSTATE_END_OF_LIST()
}
};
static void xen_gnttab_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = xen_gnttab_realize;
dc->vmsd = &xen_gnttab_vmstate;
}
static const TypeInfo xen_gnttab_info = {
.name = TYPE_XEN_GNTTAB,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(XenGnttabState),
.class_init = xen_gnttab_class_init,
};
void xen_gnttab_create(void)
{
xen_gnttab_singleton = XEN_GNTTAB(sysbus_create_simple(TYPE_XEN_GNTTAB,
-1, NULL));
}
static void xen_gnttab_register_types(void)
{
type_register_static(&xen_gnttab_info);
}
type_init(xen_gnttab_register_types)
int xen_gnttab_map_page(uint64_t idx, uint64_t gfn)
{
XenGnttabState *s = xen_gnttab_singleton;
uint64_t gpa = gfn << XEN_PAGE_SHIFT;
if (!s) {
return -ENOTSUP;
}
if (idx >= s->max_frames) {
return -EINVAL;
}
QEMU_IOTHREAD_LOCK_GUARD();
QEMU_LOCK_GUARD(&s->gnt_lock);
xen_overlay_do_map_page(&s->gnt_aliases[idx], gpa);
s->gnt_frame_gpas[idx] = gpa;
if (s->nr_frames <= idx) {
s->nr_frames = idx + 1;
}
return 0;
}
int xen_gnttab_set_version_op(struct gnttab_set_version *set)
{
int ret;
switch (set->version) {
case 1:
ret = 0;
break;
case 2:
/* Behave as before set_version was introduced. */
ret = -ENOSYS;
break;
default:
ret = -EINVAL;
}
set->version = 1;
return ret;
}
int xen_gnttab_get_version_op(struct gnttab_get_version *get)
{
if (get->dom != DOMID_SELF && get->dom != xen_domid) {
return -ESRCH;
}
get->version = 1;
return 0;
}
int xen_gnttab_query_size_op(struct gnttab_query_size *size)
{
XenGnttabState *s = xen_gnttab_singleton;
if (!s) {
return -ENOTSUP;
}
if (size->dom != DOMID_SELF && size->dom != xen_domid) {
size->status = GNTST_bad_domain;
return 0;
}
size->status = GNTST_okay;
size->nr_frames = s->nr_frames;
size->max_nr_frames = s->max_frames;
return 0;
}

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/*
* QEMU Xen emulation: Grant table support
*
* Copyright © 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Authors: David Woodhouse <dwmw2@infradead.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef QEMU_XEN_GNTTAB_H
#define QEMU_XEN_GNTTAB_H
void xen_gnttab_create(void);
int xen_gnttab_map_page(uint64_t idx, uint64_t gfn);
struct gnttab_set_version;
struct gnttab_get_version;
struct gnttab_query_size;
int xen_gnttab_set_version_op(struct gnttab_set_version *set);
int xen_gnttab_get_version_op(struct gnttab_get_version *get);
int xen_gnttab_query_size_op(struct gnttab_query_size *size);
#endif /* QEMU_XEN_GNTTAB_H */

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/*
* QEMU Xen emulation: Shared/overlay pages support
*
* Copyright © 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Authors: David Woodhouse <dwmw2@infradead.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
#include "qemu/module.h"
#include "qemu/main-loop.h"
#include "qapi/error.h"
#include "qom/object.h"
#include "exec/target_page.h"
#include "exec/address-spaces.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/xen/xen.h"
#include "xen_overlay.h"
#include "sysemu/kvm.h"
#include "sysemu/kvm_xen.h"
#include <linux/kvm.h>
#include "hw/xen/interface/memory.h"
#define TYPE_XEN_OVERLAY "xen-overlay"
OBJECT_DECLARE_SIMPLE_TYPE(XenOverlayState, XEN_OVERLAY)
#define XEN_PAGE_SHIFT 12
#define XEN_PAGE_SIZE (1ULL << XEN_PAGE_SHIFT)
struct XenOverlayState {
/*< private >*/
SysBusDevice busdev;
/*< public >*/
MemoryRegion shinfo_mem;
void *shinfo_ptr;
uint64_t shinfo_gpa;
bool long_mode;
};
struct XenOverlayState *xen_overlay_singleton;
void xen_overlay_do_map_page(MemoryRegion *page, uint64_t gpa)
{
/*
* Xen allows guests to map the same page as many times as it likes
* into guest physical frames. We don't, because it would be hard
* to track and restore them all. One mapping of each page is
* perfectly sufficient for all known guests... and we've tested
* that theory on a few now in other implementations. dwmw2.
*/
if (memory_region_is_mapped(page)) {
if (gpa == INVALID_GPA) {
memory_region_del_subregion(get_system_memory(), page);
} else {
/* Just move it */
memory_region_set_address(page, gpa);
}
} else if (gpa != INVALID_GPA) {
memory_region_add_subregion_overlap(get_system_memory(), gpa, page, 0);
}
}
/* KVM is the only existing back end for now. Let's not overengineer it yet. */
static int xen_overlay_set_be_shinfo(uint64_t gfn)
{
struct kvm_xen_hvm_attr xa = {
.type = KVM_XEN_ATTR_TYPE_SHARED_INFO,
.u.shared_info.gfn = gfn,
};
return kvm_vm_ioctl(kvm_state, KVM_XEN_HVM_SET_ATTR, &xa);
}
static void xen_overlay_realize(DeviceState *dev, Error **errp)
{
XenOverlayState *s = XEN_OVERLAY(dev);
if (xen_mode != XEN_EMULATE) {
error_setg(errp, "Xen overlay page support is for Xen emulation");
return;
}
memory_region_init_ram(&s->shinfo_mem, OBJECT(dev), "xen:shared_info",
XEN_PAGE_SIZE, &error_abort);
memory_region_set_enabled(&s->shinfo_mem, true);
s->shinfo_ptr = memory_region_get_ram_ptr(&s->shinfo_mem);
s->shinfo_gpa = INVALID_GPA;
s->long_mode = false;
memset(s->shinfo_ptr, 0, XEN_PAGE_SIZE);
}
static int xen_overlay_pre_save(void *opaque)
{
/*
* Fetch the kernel's idea of long_mode to avoid the race condition
* where the guest has set the hypercall page up in 64-bit mode but
* not yet made a hypercall by the time migration happens, so qemu
* hasn't yet noticed.
*/
return xen_sync_long_mode();
}
static int xen_overlay_post_load(void *opaque, int version_id)
{
XenOverlayState *s = opaque;
if (s->shinfo_gpa != INVALID_GPA) {
xen_overlay_do_map_page(&s->shinfo_mem, s->shinfo_gpa);
xen_overlay_set_be_shinfo(s->shinfo_gpa >> XEN_PAGE_SHIFT);
}
if (s->long_mode) {
xen_set_long_mode(true);
}
return 0;
}
static bool xen_overlay_is_needed(void *opaque)
{
return xen_mode == XEN_EMULATE;
}
static const VMStateDescription xen_overlay_vmstate = {
.name = "xen_overlay",
.version_id = 1,
.minimum_version_id = 1,
.needed = xen_overlay_is_needed,
.pre_save = xen_overlay_pre_save,
.post_load = xen_overlay_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT64(shinfo_gpa, XenOverlayState),
VMSTATE_BOOL(long_mode, XenOverlayState),
VMSTATE_END_OF_LIST()
}
};
static void xen_overlay_reset(DeviceState *dev)
{
kvm_xen_soft_reset();
}
static void xen_overlay_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = xen_overlay_reset;
dc->realize = xen_overlay_realize;
dc->vmsd = &xen_overlay_vmstate;
}
static const TypeInfo xen_overlay_info = {
.name = TYPE_XEN_OVERLAY,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(XenOverlayState),
.class_init = xen_overlay_class_init,
};
void xen_overlay_create(void)
{
xen_overlay_singleton = XEN_OVERLAY(sysbus_create_simple(TYPE_XEN_OVERLAY,
-1, NULL));
/* If xen_domid wasn't explicitly set, at least make sure it isn't zero. */
if (xen_domid == DOMID_QEMU) {
xen_domid = 1;
};
}
static void xen_overlay_register_types(void)
{
type_register_static(&xen_overlay_info);
}
type_init(xen_overlay_register_types)
int xen_overlay_map_shinfo_page(uint64_t gpa)
{
XenOverlayState *s = xen_overlay_singleton;
int ret;
if (!s) {
return -ENOENT;
}
assert(qemu_mutex_iothread_locked());
if (s->shinfo_gpa) {
/* If removing shinfo page, turn the kernel magic off first */
ret = xen_overlay_set_be_shinfo(INVALID_GFN);
if (ret) {
return ret;
}
}
xen_overlay_do_map_page(&s->shinfo_mem, gpa);
if (gpa != INVALID_GPA) {
ret = xen_overlay_set_be_shinfo(gpa >> XEN_PAGE_SHIFT);
if (ret) {
return ret;
}
}
s->shinfo_gpa = gpa;
return 0;
}
void *xen_overlay_get_shinfo_ptr(void)
{
XenOverlayState *s = xen_overlay_singleton;
if (!s) {
return NULL;
}
return s->shinfo_ptr;
}
int xen_sync_long_mode(void)
{
int ret;
struct kvm_xen_hvm_attr xa = {
.type = KVM_XEN_ATTR_TYPE_LONG_MODE,
};
if (!xen_overlay_singleton) {
return -ENOENT;
}
ret = kvm_vm_ioctl(kvm_state, KVM_XEN_HVM_GET_ATTR, &xa);
if (!ret) {
xen_overlay_singleton->long_mode = xa.u.long_mode;
}
return ret;
}
int xen_set_long_mode(bool long_mode)
{
int ret;
struct kvm_xen_hvm_attr xa = {
.type = KVM_XEN_ATTR_TYPE_LONG_MODE,
.u.long_mode = long_mode,
};
if (!xen_overlay_singleton) {
return -ENOENT;
}
ret = kvm_vm_ioctl(kvm_state, KVM_XEN_HVM_SET_ATTR, &xa);
if (!ret) {
xen_overlay_singleton->long_mode = xa.u.long_mode;
}
return ret;
}
bool xen_is_long_mode(void)
{
return xen_overlay_singleton && xen_overlay_singleton->long_mode;
}

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/*
* QEMU Xen emulation: Shared/overlay pages support
*
* Copyright © 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Authors: David Woodhouse <dwmw2@infradead.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef QEMU_XEN_OVERLAY_H
#define QEMU_XEN_OVERLAY_H
void xen_overlay_create(void);
int xen_overlay_map_shinfo_page(uint64_t gpa);
void *xen_overlay_get_shinfo_ptr(void);
int xen_sync_long_mode(void);
int xen_set_long_mode(bool long_mode);
bool xen_is_long_mode(void);
void xen_overlay_do_map_page(MemoryRegion *page, uint64_t gpa);
#endif /* QEMU_XEN_OVERLAY_H */

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/*
* QEMU Xen emulation: Shared/overlay pages support
*
* Copyright © 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Authors: David Woodhouse <dwmw2@infradead.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
#include "qemu/module.h"
#include "qemu/main-loop.h"
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qom/object.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/xen/xen.h"
#include "xen_overlay.h"
#include "xen_evtchn.h"
#include "xen_xenstore.h"
#include "sysemu/kvm.h"
#include "sysemu/kvm_xen.h"
#include "hw/xen/interface/io/xs_wire.h"
#include "hw/xen/interface/event_channel.h"
#define TYPE_XEN_XENSTORE "xen-xenstore"
OBJECT_DECLARE_SIMPLE_TYPE(XenXenstoreState, XEN_XENSTORE)
#define XEN_PAGE_SHIFT 12
#define XEN_PAGE_SIZE (1ULL << XEN_PAGE_SHIFT)
#define ENTRIES_PER_FRAME_V1 (XEN_PAGE_SIZE / sizeof(grant_entry_v1_t))
#define ENTRIES_PER_FRAME_V2 (XEN_PAGE_SIZE / sizeof(grant_entry_v2_t))
#define XENSTORE_HEADER_SIZE ((unsigned int)sizeof(struct xsd_sockmsg))
struct XenXenstoreState {
/*< private >*/
SysBusDevice busdev;
/*< public >*/
MemoryRegion xenstore_page;
struct xenstore_domain_interface *xs;
uint8_t req_data[XENSTORE_HEADER_SIZE + XENSTORE_PAYLOAD_MAX];
uint8_t rsp_data[XENSTORE_HEADER_SIZE + XENSTORE_PAYLOAD_MAX];
uint32_t req_offset;
uint32_t rsp_offset;
bool rsp_pending;
bool fatal_error;
evtchn_port_t guest_port;
evtchn_port_t be_port;
struct xenevtchn_handle *eh;
};
struct XenXenstoreState *xen_xenstore_singleton;
static void xen_xenstore_event(void *opaque);
static void xen_xenstore_realize(DeviceState *dev, Error **errp)
{
XenXenstoreState *s = XEN_XENSTORE(dev);
if (xen_mode != XEN_EMULATE) {
error_setg(errp, "Xen xenstore support is for Xen emulation");
return;
}
memory_region_init_ram(&s->xenstore_page, OBJECT(dev), "xen:xenstore_page",
XEN_PAGE_SIZE, &error_abort);
memory_region_set_enabled(&s->xenstore_page, true);
s->xs = memory_region_get_ram_ptr(&s->xenstore_page);
memset(s->xs, 0, XEN_PAGE_SIZE);
/* We can't map it this early as KVM isn't ready */
xen_xenstore_singleton = s;
s->eh = xen_be_evtchn_open();
if (!s->eh) {
error_setg(errp, "Xenstore evtchn port init failed");
return;
}
aio_set_fd_handler(qemu_get_aio_context(), xen_be_evtchn_fd(s->eh), true,
xen_xenstore_event, NULL, NULL, NULL, s);
}
static bool xen_xenstore_is_needed(void *opaque)
{
return xen_mode == XEN_EMULATE;
}
static int xen_xenstore_pre_save(void *opaque)
{
XenXenstoreState *s = opaque;
if (s->eh) {
s->guest_port = xen_be_evtchn_get_guest_port(s->eh);
}
return 0;
}
static int xen_xenstore_post_load(void *opaque, int ver)
{
XenXenstoreState *s = opaque;
/*
* As qemu/dom0, rebind to the guest's port. The Windows drivers may
* unbind the XenStore evtchn and rebind to it, having obtained the
* "remote" port through EVTCHNOP_status. In the case that migration
* occurs while it's unbound, the "remote" port needs to be the same
* as before so that the guest can find it, but should remain unbound.
*/
if (s->guest_port) {
int be_port = xen_be_evtchn_bind_interdomain(s->eh, xen_domid,
s->guest_port);
if (be_port < 0) {
return be_port;
}
s->be_port = be_port;
}
return 0;
}
static const VMStateDescription xen_xenstore_vmstate = {
.name = "xen_xenstore",
.version_id = 1,
.minimum_version_id = 1,
.needed = xen_xenstore_is_needed,
.pre_save = xen_xenstore_pre_save,
.post_load = xen_xenstore_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT8_ARRAY(req_data, XenXenstoreState,
sizeof_field(XenXenstoreState, req_data)),
VMSTATE_UINT8_ARRAY(rsp_data, XenXenstoreState,
sizeof_field(XenXenstoreState, rsp_data)),
VMSTATE_UINT32(req_offset, XenXenstoreState),
VMSTATE_UINT32(rsp_offset, XenXenstoreState),
VMSTATE_BOOL(rsp_pending, XenXenstoreState),
VMSTATE_UINT32(guest_port, XenXenstoreState),
VMSTATE_BOOL(fatal_error, XenXenstoreState),
VMSTATE_END_OF_LIST()
}
};
static void xen_xenstore_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = xen_xenstore_realize;
dc->vmsd = &xen_xenstore_vmstate;
}
static const TypeInfo xen_xenstore_info = {
.name = TYPE_XEN_XENSTORE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(XenXenstoreState),
.class_init = xen_xenstore_class_init,
};
void xen_xenstore_create(void)
{
DeviceState *dev = sysbus_create_simple(TYPE_XEN_XENSTORE, -1, NULL);
xen_xenstore_singleton = XEN_XENSTORE(dev);
/*
* Defer the init (xen_xenstore_reset()) until KVM is set up and the
* overlay page can be mapped.
*/
}
static void xen_xenstore_register_types(void)
{
type_register_static(&xen_xenstore_info);
}
type_init(xen_xenstore_register_types)
uint16_t xen_xenstore_get_port(void)
{
XenXenstoreState *s = xen_xenstore_singleton;
if (!s) {
return 0;
}
return s->guest_port;
}
static bool req_pending(XenXenstoreState *s)
{
struct xsd_sockmsg *req = (struct xsd_sockmsg *)s->req_data;
return s->req_offset == XENSTORE_HEADER_SIZE + req->len;
}
static void reset_req(XenXenstoreState *s)
{
memset(s->req_data, 0, sizeof(s->req_data));
s->req_offset = 0;
}
static void reset_rsp(XenXenstoreState *s)
{
s->rsp_pending = false;
memset(s->rsp_data, 0, sizeof(s->rsp_data));
s->rsp_offset = 0;
}
static void process_req(XenXenstoreState *s)
{
struct xsd_sockmsg *req = (struct xsd_sockmsg *)s->req_data;
struct xsd_sockmsg *rsp = (struct xsd_sockmsg *)s->rsp_data;
const char enosys[] = "ENOSYS";
assert(req_pending(s));
assert(!s->rsp_pending);
rsp->type = XS_ERROR;
rsp->req_id = req->req_id;
rsp->tx_id = req->tx_id;
rsp->len = sizeof(enosys);
memcpy((void *)&rsp[1], enosys, sizeof(enosys));
s->rsp_pending = true;
reset_req(s);
}
static unsigned int copy_from_ring(XenXenstoreState *s, uint8_t *ptr,
unsigned int len)
{
if (!len) {
return 0;
}
XENSTORE_RING_IDX prod = qatomic_read(&s->xs->req_prod);
XENSTORE_RING_IDX cons = qatomic_read(&s->xs->req_cons);
unsigned int copied = 0;
/* Ensure the ring contents don't cross the req_prod access. */
smp_rmb();
while (len) {
unsigned int avail = prod - cons;
unsigned int offset = MASK_XENSTORE_IDX(cons);
unsigned int copylen = avail;
if (avail > XENSTORE_RING_SIZE) {
error_report("XenStore ring handling error");
s->fatal_error = true;
break;
} else if (avail == 0) {
break;
}
if (copylen > len) {
copylen = len;
}
if (copylen > XENSTORE_RING_SIZE - offset) {
copylen = XENSTORE_RING_SIZE - offset;
}
memcpy(ptr, &s->xs->req[offset], copylen);
copied += copylen;
ptr += copylen;
len -= copylen;
cons += copylen;
}
/*
* Not sure this ever mattered except on Alpha, but this barrier
* is to ensure that the update to req_cons is globally visible
* only after we have consumed all the data from the ring, and we
* don't end up seeing data written to the ring *after* the other
* end sees the update and writes more to the ring. Xen's own
* xenstored has the same barrier here (although with no comment
* at all, obviously, because it's Xen code).
*/
smp_mb();
qatomic_set(&s->xs->req_cons, cons);
return copied;
}
static unsigned int copy_to_ring(XenXenstoreState *s, uint8_t *ptr,
unsigned int len)
{
if (!len) {
return 0;
}
XENSTORE_RING_IDX cons = qatomic_read(&s->xs->rsp_cons);
XENSTORE_RING_IDX prod = qatomic_read(&s->xs->rsp_prod);
unsigned int copied = 0;
/*
* This matches the barrier in copy_to_ring() (or the guest's
* equivalent) betweem writing the data to the ring and updating
* rsp_prod. It protects against the pathological case (which
* again I think never happened except on Alpha) where our
* subsequent writes to the ring could *cross* the read of
* rsp_cons and the guest could see the new data when it was
* intending to read the old.
*/
smp_mb();
while (len) {
unsigned int avail = cons + XENSTORE_RING_SIZE - prod;
unsigned int offset = MASK_XENSTORE_IDX(prod);
unsigned int copylen = len;
if (avail > XENSTORE_RING_SIZE) {
error_report("XenStore ring handling error");
s->fatal_error = true;
break;
} else if (avail == 0) {
break;
}
if (copylen > avail) {
copylen = avail;
}
if (copylen > XENSTORE_RING_SIZE - offset) {
copylen = XENSTORE_RING_SIZE - offset;
}
memcpy(&s->xs->rsp[offset], ptr, copylen);
copied += copylen;
ptr += copylen;
len -= copylen;
prod += copylen;
}
/* Ensure the ring contents are seen before rsp_prod update. */
smp_wmb();
qatomic_set(&s->xs->rsp_prod, prod);
return copied;
}
static unsigned int get_req(XenXenstoreState *s)
{
unsigned int copied = 0;
if (s->fatal_error) {
return 0;
}
assert(!req_pending(s));
if (s->req_offset < XENSTORE_HEADER_SIZE) {
void *ptr = s->req_data + s->req_offset;
unsigned int len = XENSTORE_HEADER_SIZE;
unsigned int copylen = copy_from_ring(s, ptr, len);
copied += copylen;
s->req_offset += copylen;
}
if (s->req_offset >= XENSTORE_HEADER_SIZE) {
struct xsd_sockmsg *req = (struct xsd_sockmsg *)s->req_data;
if (req->len > (uint32_t)XENSTORE_PAYLOAD_MAX) {
error_report("Illegal XenStore request");
s->fatal_error = true;
return 0;
}
void *ptr = s->req_data + s->req_offset;
unsigned int len = XENSTORE_HEADER_SIZE + req->len - s->req_offset;
unsigned int copylen = copy_from_ring(s, ptr, len);
copied += copylen;
s->req_offset += copylen;
}
return copied;
}
static unsigned int put_rsp(XenXenstoreState *s)
{
if (s->fatal_error) {
return 0;
}
assert(s->rsp_pending);
struct xsd_sockmsg *rsp = (struct xsd_sockmsg *)s->rsp_data;
assert(s->rsp_offset < XENSTORE_HEADER_SIZE + rsp->len);
void *ptr = s->rsp_data + s->rsp_offset;
unsigned int len = XENSTORE_HEADER_SIZE + rsp->len - s->rsp_offset;
unsigned int copylen = copy_to_ring(s, ptr, len);
s->rsp_offset += copylen;
/* Have we produced a complete response? */
if (s->rsp_offset == XENSTORE_HEADER_SIZE + rsp->len) {
reset_rsp(s);
}
return copylen;
}
static void xen_xenstore_event(void *opaque)
{
XenXenstoreState *s = opaque;
evtchn_port_t port = xen_be_evtchn_pending(s->eh);
unsigned int copied_to, copied_from;
bool processed, notify = false;
if (port != s->be_port) {
return;
}
/* We know this is a no-op. */
xen_be_evtchn_unmask(s->eh, port);
do {
copied_to = copied_from = 0;
processed = false;
if (s->rsp_pending) {
copied_to = put_rsp(s);
}
if (!req_pending(s)) {
copied_from = get_req(s);
}
if (req_pending(s) && !s->rsp_pending) {
process_req(s);
processed = true;
}
notify |= copied_to || copied_from;
} while (copied_to || copied_from || processed);
if (notify) {
xen_be_evtchn_notify(s->eh, s->be_port);
}
}
static void alloc_guest_port(XenXenstoreState *s)
{
struct evtchn_alloc_unbound alloc = {
.dom = DOMID_SELF,
.remote_dom = DOMID_QEMU,
};
if (!xen_evtchn_alloc_unbound_op(&alloc)) {
s->guest_port = alloc.port;
}
}
int xen_xenstore_reset(void)
{
XenXenstoreState *s = xen_xenstore_singleton;
int err;
if (!s) {
return -ENOTSUP;
}
s->req_offset = s->rsp_offset = 0;
s->rsp_pending = false;
if (!memory_region_is_mapped(&s->xenstore_page)) {
uint64_t gpa = XEN_SPECIAL_PFN(XENSTORE) << TARGET_PAGE_BITS;
xen_overlay_do_map_page(&s->xenstore_page, gpa);
}
alloc_guest_port(s);
/*
* As qemu/dom0, bind to the guest's port. For incoming migration, this
* will be unbound as the guest's evtchn table is overwritten. We then
* rebind to the correct guest port in xen_xenstore_post_load().
*/
err = xen_be_evtchn_bind_interdomain(s->eh, xen_domid, s->guest_port);
if (err < 0) {
return err;
}
s->be_port = err;
return 0;
}

20
hw/i386/kvm/xen_xenstore.h Normal file
View File

@ -0,0 +1,20 @@
/*
* QEMU Xen emulation: Xenstore emulation
*
* Copyright © 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Authors: David Woodhouse <dwmw2@infradead.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef QEMU_XEN_XENSTORE_H
#define QEMU_XEN_XENSTORE_H
void xen_xenstore_create(void);
int xen_xenstore_reset(void);
uint16_t xen_xenstore_get_port(void);
#endif /* QEMU_XEN_XENSTORE_H */

30
hw/i386/microvm.c
View File

@ -57,14 +57,14 @@
#define MICROVM_QBOOT_FILENAME "qboot.rom"
#define MICROVM_BIOS_FILENAME "bios-microvm.bin"
static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s)
static void microvm_set_rtc(MicrovmMachineState *mms, MC146818RtcState *s)
{
X86MachineState *x86ms = X86_MACHINE(mms);
int val;
val = MIN(x86ms->below_4g_mem_size / KiB, 640);
rtc_set_memory(s, 0x15, val);
rtc_set_memory(s, 0x16, val >> 8);
mc146818rtc_set_cmos_data(s, 0x15, val);
mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
/* extended memory (next 64MiB) */
if (x86ms->below_4g_mem_size > 1 * MiB) {
val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
@ -74,10 +74,10 @@ static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s)
if (val > 65535) {
val = 65535;
}
rtc_set_memory(s, 0x17, val);
rtc_set_memory(s, 0x18, val >> 8);
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
mc146818rtc_set_cmos_data(s, 0x17, val);
mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
mc146818rtc_set_cmos_data(s, 0x30, val);
mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
/* memory between 16MiB and 4GiB */
if (x86ms->below_4g_mem_size > 16 * MiB) {
val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
@ -87,13 +87,13 @@ static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s)
if (val > 65535) {
val = 65535;
}
rtc_set_memory(s, 0x34, val);
rtc_set_memory(s, 0x35, val >> 8);
mc146818rtc_set_cmos_data(s, 0x34, val);
mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
/* memory above 4GiB */
val = x86ms->above_4g_mem_size / 65536;
rtc_set_memory(s, 0x5b, val);
rtc_set_memory(s, 0x5c, val >> 8);
rtc_set_memory(s, 0x5d, val >> 16);
mc146818rtc_set_cmos_data(s, 0x5b, val);
mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
}
static void create_gpex(MicrovmMachineState *mms)
@ -161,7 +161,6 @@ static void microvm_devices_init(MicrovmMachineState *mms)
const char *default_firmware;
X86MachineState *x86ms = X86_MACHINE(mms);
ISABus *isa_bus;
ISADevice *rtc_state;
GSIState *gsi_state;
int ioapics;
int i;
@ -174,7 +173,7 @@ static void microvm_devices_init(MicrovmMachineState *mms)
isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io(),
&error_abort);
isa_bus_irqs(isa_bus, x86ms->gsi);
isa_bus_register_input_irqs(isa_bus, x86ms->gsi);
ioapic_init_gsi(gsi_state, "machine");
if (ioapics > 1) {
@ -267,8 +266,7 @@ static void microvm_devices_init(MicrovmMachineState *mms)
if (mms->rtc == ON_OFF_AUTO_ON ||
(mms->rtc == ON_OFF_AUTO_AUTO && !kvm_enabled())) {
rtc_state = mc146818_rtc_init(isa_bus, 2000, NULL);
microvm_set_rtc(mms, rtc_state);
microvm_set_rtc(mms, mc146818_rtc_init(isa_bus, 2000, NULL));
}
if (mms->isa_serial) {

109
hw/i386/pc.c
View File

@ -28,13 +28,13 @@
#include "hw/i386/pc.h"
#include "hw/char/serial.h"
#include "hw/char/parallel.h"
#include "hw/i386/apic.h"
#include "hw/i386/topology.h"
#include "hw/i386/fw_cfg.h"
#include "hw/i386/vmport.h"
#include "sysemu/cpus.h"
#include "hw/block/fdc.h"
#include "hw/ide.h"
#include "hw/ide/internal.h"
#include "hw/ide/isa.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-bridge/pci_expander_bridge.h"
@ -47,6 +47,7 @@
#include "multiboot.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/intc/i8259.h"
#include "hw/intc/ioapic.h"
#include "hw/timer/i8254.h"
#include "hw/input/i8042.h"
#include "hw/irq.h"
@ -89,6 +90,10 @@
#include "hw/virtio/virtio-iommu.h"
#include "hw/virtio/virtio-pmem-pci.h"
#include "hw/virtio/virtio-mem-pci.h"
#include "hw/i386/kvm/xen_overlay.h"
#include "hw/i386/kvm/xen_evtchn.h"
#include "hw/i386/kvm/xen_gnttab.h"
#include "hw/i386/kvm/xen_xenstore.h"
#include "hw/mem/memory-device.h"
#include "sysemu/replay.h"
#include "target/i386/cpu.h"
@ -405,7 +410,7 @@ GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
if (kvm_ioapic_in_kernel()) {
kvm_pc_setup_irq_routing(pci_enabled);
}
*irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
*irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
return s;
}
@ -438,19 +443,19 @@ static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
#define REG_EQUIPMENT_BYTE 0x14
static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
int16_t cylinders, int8_t heads, int8_t sectors)
{
rtc_set_memory(s, type_ofs, 47);
rtc_set_memory(s, info_ofs, cylinders);
rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
rtc_set_memory(s, info_ofs + 2, heads);
rtc_set_memory(s, info_ofs + 3, 0xff);
rtc_set_memory(s, info_ofs + 4, 0xff);
rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
rtc_set_memory(s, info_ofs + 6, cylinders);
rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
rtc_set_memory(s, info_ofs + 8, sectors);
mc146818rtc_set_cmos_data(s, type_ofs, 47);
mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
}
/* convert boot_device letter to something recognizable by the bios */
@ -470,7 +475,8 @@ static int boot_device2nibble(char boot_device)
return 0;
}
static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
static void set_boot_dev(MC146818RtcState *s, const char *boot_device,
Error **errp)
{
#define PC_MAX_BOOT_DEVICES 3
int nbds, bds[3] = { 0, };
@ -489,8 +495,8 @@ static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
return;
}
}
rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
}
static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
@ -498,7 +504,7 @@ static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
set_boot_dev(opaque, boot_device, errp);
}
static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
{
int val, nb, i;
FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
@ -512,9 +518,9 @@ static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
}
val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
cmos_get_fd_drive_type(fd_type[1]);
rtc_set_memory(rtc_state, 0x10, val);
mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
nb = 0;
if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
nb++;
@ -532,11 +538,11 @@ static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
val |= 0x41; /* 2 drives, ready for boot */
break;
}
rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
}
typedef struct pc_cmos_init_late_arg {
ISADevice *rtc_state;
MC146818RtcState *rtc_state;
BusState *idebus[2];
} pc_cmos_init_late_arg;
@ -603,7 +609,7 @@ static ISADevice *pc_find_fdc0(void)
static void pc_cmos_init_late(void *opaque)
{
pc_cmos_init_late_arg *arg = opaque;
ISADevice *s = arg->rtc_state;
MC146818RtcState *s = arg->rtc_state;
int16_t cylinders;
int8_t heads, sectors;
int val;
@ -620,7 +626,7 @@ static void pc_cmos_init_late(void *opaque)
cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
val |= 0x0f;
}
rtc_set_memory(s, 0x12, val);
mc146818rtc_set_cmos_data(s, 0x12, val);
val = 0;
for (i = 0; i < 4; i++) {
@ -636,7 +642,7 @@ static void pc_cmos_init_late(void *opaque)
val |= trans << (i * 2);
}
}
rtc_set_memory(s, 0x39, val);
mc146818rtc_set_cmos_data(s, 0x39, val);
pc_cmos_init_floppy(s, pc_find_fdc0());
@ -645,19 +651,20 @@ static void pc_cmos_init_late(void *opaque)
void pc_cmos_init(PCMachineState *pcms,
BusState *idebus0, BusState *idebus1,
ISADevice *s)
ISADevice *rtc)
{
int val;
static pc_cmos_init_late_arg arg;
X86MachineState *x86ms = X86_MACHINE(pcms);
MC146818RtcState *s = MC146818_RTC(rtc);
/* various important CMOS locations needed by PC/Bochs bios */
/* memory size */
/* base memory (first MiB) */
val = MIN(x86ms->below_4g_mem_size / KiB, 640);
rtc_set_memory(s, 0x15, val);
rtc_set_memory(s, 0x16, val >> 8);
mc146818rtc_set_cmos_data(s, 0x15, val);
mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
/* extended memory (next 64MiB) */
if (x86ms->below_4g_mem_size > 1 * MiB) {
val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
@ -666,10 +673,10 @@ void pc_cmos_init(PCMachineState *pcms,
}
if (val > 65535)
val = 65535;
rtc_set_memory(s, 0x17, val);
rtc_set_memory(s, 0x18, val >> 8);
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
mc146818rtc_set_cmos_data(s, 0x17, val);
mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
mc146818rtc_set_cmos_data(s, 0x30, val);
mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
/* memory between 16MiB and 4GiB */
if (x86ms->below_4g_mem_size > 16 * MiB) {
val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
@ -678,13 +685,13 @@ void pc_cmos_init(PCMachineState *pcms,
}
if (val > 65535)
val = 65535;
rtc_set_memory(s, 0x34, val);
rtc_set_memory(s, 0x35, val >> 8);
mc146818rtc_set_cmos_data(s, 0x34, val);
mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
/* memory above 4GiB */
val = x86ms->above_4g_mem_size / 65536;
rtc_set_memory(s, 0x5b, val);
rtc_set_memory(s, 0x5c, val >> 8);
rtc_set_memory(s, 0x5d, val >> 16);
mc146818rtc_set_cmos_data(s, 0x5b, val);
mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
object_property_add_link(OBJECT(pcms), "rtc_state",
TYPE_ISA_DEVICE,
@ -699,7 +706,7 @@ void pc_cmos_init(PCMachineState *pcms,
val = 0;
val |= 0x02; /* FPU is there */
val |= 0x04; /* PS/2 mouse installed */
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
/* hard drives and FDC */
arg.rtc_state = s;
@ -1296,14 +1303,23 @@ void pc_basic_device_init(struct PCMachineState *pcms,
sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
for (i = 0; i < GSI_NUM_PINS; i++) {
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
}
pit_isa_irq = -1;
pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
}
*rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
*rtc_state = ISA_DEVICE(mc146818_rtc_init(isa_bus, 2000, rtc_irq));
#ifdef CONFIG_XEN_EMU
if (xen_mode == XEN_EMULATE) {
xen_evtchn_connect_gsis(gsi);
if (pcms->bus) {
pci_create_simple(pcms->bus, -1, "xen-platform");
}
}
#endif
qemu_register_boot_set(pc_boot_set, *rtc_state);
@ -1843,6 +1859,19 @@ static void pc_machine_initfn(Object *obj)
cxl_machine_init(obj, &pcms->cxl_devices_state);
}
int pc_machine_kvm_type(MachineState *machine, const char *kvm_type)
{
#ifdef CONFIG_XEN_EMU
if (xen_mode == XEN_EMULATE) {
xen_overlay_create();
xen_evtchn_create();
xen_gnttab_create();
xen_xenstore_create();
}
#endif
return 0;
}
static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
{
CPUState *cs;

3
hw/i386/pc_piix.c
View File

@ -39,6 +39,7 @@
#include "hw/pci/pci_ids.h"
#include "hw/usb.h"
#include "net/net.h"
#include "hw/ide/isa.h"
#include "hw/ide/pci.h"
#include "hw/ide/piix.h"
#include "hw/irq.h"
@ -246,7 +247,7 @@ static void pc_init1(MachineState *machine,
i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
}
isa_bus_irqs(isa_bus, x86ms->gsi);
isa_bus_register_input_irqs(isa_bus, x86ms->gsi);
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
pc_i8259_create(isa_bus, gsi_state->i8259_irq);

34
hw/i386/pc_q35.c
View File

@ -40,13 +40,14 @@
#include "hw/qdev-properties.h"
#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
#include "hw/i386/ich9.h"
#include "hw/i386/amd_iommu.h"
#include "hw/i386/intel_iommu.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/intc/ioapic.h"
#include "hw/southbridge/ich9.h"
#include "hw/usb.h"
#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
@ -132,7 +133,6 @@ static void pc_q35_init(MachineState *machine)
GSIState *gsi_state;
ISABus *isa_bus;
int i;
ICH9LPCState *ich9_lpc;
PCIDevice *ahci;
ram_addr_t lowmem;
DriveInfo *hd[MAX_SATA_PORTS];
@ -236,9 +236,11 @@ static void pc_q35_init(MachineState *machine)
phb = PCI_HOST_BRIDGE(q35_host);
host_bus = phb->bus;
/* create ISA bus */
lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
ICH9_LPC_FUNC), true,
TYPE_ICH9_LPC_DEVICE);
lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true,
TYPE_ICH9_LPC_DEVICE);
qdev_prop_set_bit(DEVICE(lpc), "smm-enabled",
x86_machine_is_smm_enabled(x86ms));
pci_realize_and_unref(lpc, host_bus, &error_fatal);
object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
TYPE_HOTPLUG_HANDLER,
@ -265,15 +267,11 @@ static void pc_q35_init(MachineState *machine)
/* irq lines */
gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
ich9_lpc = ICH9_LPC_DEVICE(lpc);
lpc_dev = DEVICE(lpc);
for (i = 0; i < GSI_NUM_PINS; i++) {
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc, ICH9_LPC_NB_PIRQS);
pci_bus_map_irqs(host_bus, ich9_lpc_map_irq);
pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
isa_bus = ich9_lpc->isa_bus;
isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0"));
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
pc_i8259_create(isa_bus, gsi_state->i8259_irq);
@ -296,9 +294,6 @@ static void pc_q35_init(MachineState *machine)
pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
0xff0104);
/* connect pm stuff to lpc */
ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms));
if (pcms->sata_enabled) {
/* ahci and SATA device, for q35 1 ahci controller is built-in */
ahci = pci_create_simple_multifunction(host_bus,
@ -320,10 +315,15 @@ static void pc_q35_init(MachineState *machine)
}
if (pcms->smbus_enabled) {
PCIDevice *smb;
/* TODO: Populate SPD eeprom data. */
pcms->smbus = ich9_smb_init(host_bus,
PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
0xb100);
smb = pci_create_simple_multifunction(host_bus,
PCI_DEVFN(ICH9_SMB_DEV,
ICH9_SMB_FUNC),
true, TYPE_ICH9_SMB_DEVICE);
pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c"));
smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
}

26
hw/i386/x86.c
View File

@ -61,10 +61,15 @@
#include CONFIG_DEVICES
#include "kvm/kvm_i386.h"
#ifdef CONFIG_XEN_EMU
#include "hw/xen/xen.h"
#include "hw/i386/kvm/xen_evtchn.h"
#endif
/* Physical Address of PVH entry point read from kernel ELF NOTE */
static size_t pvh_start_addr;
inline void init_topo_info(X86CPUTopoInfo *topo_info,
static void init_topo_info(X86CPUTopoInfo *topo_info,
const X86MachineState *x86ms)
{
MachineState *ms = MACHINE(x86ms);
@ -150,17 +155,19 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
}
}
void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
void x86_rtc_set_cpus_count(ISADevice *s, uint16_t cpus_count)
{
MC146818RtcState *rtc = MC146818_RTC(s);
if (cpus_count > 0xff) {
/*
* If the number of CPUs can't be represented in 8 bits, the
* BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
* to make old BIOSes fail more predictably.
*/
rtc_set_memory(rtc, 0x5f, 0);
mc146818rtc_set_cmos_data(rtc, 0x5f, 0);
} else {
rtc_set_memory(rtc, 0x5f, cpus_count - 1);
mc146818rtc_set_cmos_data(rtc, 0x5f, cpus_count - 1);
}
}
@ -608,6 +615,17 @@ void gsi_handler(void *opaque, int n, int level)
}
/* fall through */
case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1:
#ifdef CONFIG_XEN_EMU
/*
* Xen delivers the GSI to the Legacy PIC (not that Legacy PIC
* routing actually works properly under Xen). And then to
* *either* the PIRQ handling or the I/OAPIC depending on
* whether the former wants it.
*/
if (xen_mode == XEN_EMULATE && xen_evtchn_set_gsi(n, level)) {
break;
}
#endif
qemu_set_irq(s->ioapic_irq[n], level);
break;
case IO_APIC_SECONDARY_IRQBASE

5
hw/i386/xen/meson.build
View File

@ -2,6 +2,9 @@ i386_ss.add(when: 'CONFIG_XEN', if_true: files(
'xen-hvm.c',
'xen-mapcache.c',
'xen_apic.c',
'xen_platform.c',
'xen_pvdevice.c',
))
i386_ss.add(when: 'CONFIG_XEN_BUS', if_true: files(
'xen_platform.c',
))

8
hw/i386/xen/xen-hvm.c
View File

@ -1502,13 +1502,7 @@ void xen_hvm_init_pc(PCMachineState *pcms, MemoryRegion **ram_memory)
device_listener_register(&state->device_listener);
xen_bus_init();
/* Initialize backend core & drivers */
if (xen_be_init() != 0) {
error_report("xen backend core setup failed");
goto err;
}
xen_be_register_common();
xen_be_init();
QLIST_INIT(&xen_physmap);
xen_read_physmap(state);

58
hw/i386/xen/xen_platform.c
View File

@ -25,12 +25,11 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/ide.h"
#include "hw/ide/pci.h"
#include "hw/pci/pci.h"
#include "hw/xen/xen_common.h"
#include "migration/vmstate.h"
#include "hw/xen/xen-legacy-backend.h"
#include "hw/xen/xen.h"
#include "net/net.h"
#include "trace.h"
#include "sysemu/xen.h"
#include "sysemu/block-backend.h"
@ -38,6 +37,11 @@
#include "qemu/module.h"
#include "qom/object.h"
#ifdef CONFIG_XEN
#include "hw/xen/xen_common.h"
#include "hw/xen/xen-legacy-backend.h"
#endif
//#define DEBUG_PLATFORM
#ifdef DEBUG_PLATFORM
@ -109,12 +113,25 @@ static void log_writeb(PCIXenPlatformState *s, char val)
#define _UNPLUG_NVME_DISKS 3
#define UNPLUG_NVME_DISKS (1u << _UNPLUG_NVME_DISKS)
static bool pci_device_is_passthrough(PCIDevice *d)
{
if (!strcmp(d->name, "xen-pci-passthrough")) {
return true;
}
if (xen_mode == XEN_EMULATE && !strcmp(d->name, "vfio-pci")) {
return true;
}
return false;
}
static void unplug_nic(PCIBus *b, PCIDevice *d, void *o)
{
/* We have to ignore passthrough devices */
if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
PCI_CLASS_NETWORK_ETHERNET
&& strcmp(d->name, "xen-pci-passthrough") != 0) {
&& !pci_device_is_passthrough(d)) {
object_unparent(OBJECT(d));
}
}
@ -187,9 +204,8 @@ static void unplug_disks(PCIBus *b, PCIDevice *d, void *opaque)
!(flags & UNPLUG_IDE_SCSI_DISKS);
/* We have to ignore passthrough devices */
if (!strcmp(d->name, "xen-pci-passthrough")) {
if (pci_device_is_passthrough(d))
return;
}
switch (pci_get_word(d->config + PCI_CLASS_DEVICE)) {
case PCI_CLASS_STORAGE_IDE:
@ -268,18 +284,26 @@ static void platform_fixed_ioport_writeb(void *opaque, uint32_t addr, uint32_t v
PCIXenPlatformState *s = opaque;
switch (addr) {
case 0: /* Platform flags */ {
hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?
HVMMEM_ram_ro : HVMMEM_ram_rw;
if (xen_set_mem_type(xen_domid, mem_type, 0xc0, 0x40)) {
DPRINTF("unable to change ro/rw state of ROM memory area!\n");
} else {
case 0: /* Platform flags */
if (xen_mode == XEN_EMULATE) {
/* XX: Use i440gx/q35 PAM setup to do this? */
s->flags = val & PFFLAG_ROM_LOCK;
DPRINTF("changed ro/rw state of ROM memory area. now is %s state.\n",
(mem_type == HVMMEM_ram_ro ? "ro":"rw"));
#ifdef CONFIG_XEN
} else {
hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?
HVMMEM_ram_ro : HVMMEM_ram_rw;
if (xen_set_mem_type(xen_domid, mem_type, 0xc0, 0x40)) {
DPRINTF("unable to change ro/rw state of ROM memory area!\n");
} else {
s->flags = val & PFFLAG_ROM_LOCK;
DPRINTF("changed ro/rw state of ROM memory area. now is %s state.\n",
(mem_type == HVMMEM_ram_ro ? "ro" : "rw"));
}
#endif
}
break;
}
case 2:
log_writeb(s, val);
break;
@ -497,8 +521,8 @@ static void xen_platform_realize(PCIDevice *dev, Error **errp)
uint8_t *pci_conf;
/* Device will crash on reset if xen is not initialized */
if (!xen_enabled()) {
error_setg(errp, "xen-platform device requires the Xen accelerator");
if (xen_mode == XEN_DISABLED) {
error_setg(errp, "xen-platform device requires a Xen guest");
return;
}

13
hw/ide/ahci.c
View File

@ -22,6 +22,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/msi.h"
#include "hw/pci/pci.h"
#include "hw/qdev-properties.h"
@ -1085,8 +1086,8 @@ static void execute_ncq_command(NCQTransferState *ncq_tfs)
ncq_cb, ncq_tfs);
break;
case WRITE_FPDMA_QUEUED:
trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag,
ncq_tfs->sector_count, ncq_tfs->lba);
trace_execute_ncq_command_write(ad->hba, port, ncq_tfs->tag,
ncq_tfs->sector_count, ncq_tfs->lba);
dma_acct_start(ide_state->blk, &ncq_tfs->acct,
&ncq_tfs->sglist, BLOCK_ACCT_WRITE);
ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist,
@ -1268,7 +1269,7 @@ static void handle_reg_h2d_fis(AHCIState *s, int port,
cmd->status = 0;
/* We're ready to process the command in FIS byte 2. */
ide_exec_cmd(&s->dev[port].port, cmd_fis[2]);
ide_bus_exec_cmd(&s->dev[port].port, cmd_fis[2]);
}
static int handle_cmd(AHCIState *s, int port, uint8_t slot)
@ -1553,13 +1554,13 @@ void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
AHCIDevice *ad = &s->dev[i];
ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1);
ide_init2(&ad->port, irqs[i]);
ide_bus_init_output_irq(&ad->port, irqs[i]);
ad->hba = s;
ad->port_no = i;
ad->port.dma = &ad->dma;
ad->port.dma->ops = &ahci_dma_ops;
ide_register_restart_cb(&ad->port);
ide_bus_register_restart_cb(&ad->port);
}
g_free(irqs);
}
@ -1841,7 +1842,7 @@ void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
if (hd[i] == NULL) {
continue;
}
ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
}
}

13
hw/ide/atapi.c
View File

@ -27,6 +27,7 @@
#include "hw/ide/internal.h"
#include "hw/scsi/scsi.h"
#include "sysemu/block-backend.h"
#include "scsi/constants.h"
#include "trace.h"
#define ATAPI_SECTOR_BITS (2 + BDRV_SECTOR_BITS)
@ -178,7 +179,7 @@ void ide_atapi_cmd_ok(IDEState *s)
s->status = READY_STAT | SEEK_STAT;
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
ide_transfer_stop(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
@ -190,7 +191,7 @@ void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
s->sense_key = sense_key;
s->asc = asc;
ide_transfer_stop(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
void ide_atapi_io_error(IDEState *s, int ret)
@ -253,7 +254,7 @@ void ide_atapi_cmd_reply_end(IDEState *s)
} else {
/* a new transfer is needed */
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
byte_count_limit = atapi_byte_count_limit(s);
trace_ide_atapi_cmd_reply_end_bcl(s, byte_count_limit);
size = s->packet_transfer_size;
@ -293,7 +294,7 @@ void ide_atapi_cmd_reply_end(IDEState *s)
/* end of transfer */
trace_ide_atapi_cmd_reply_end_eot(s, s->status);
ide_atapi_cmd_ok(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
/* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
@ -339,7 +340,7 @@ static void ide_atapi_cmd_check_status(IDEState *s)
s->error = MC_ERR | (UNIT_ATTENTION << 4);
s->status = ERR_STAT;
s->nsector = 0;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
/* ATAPI DMA support */
@ -383,7 +384,7 @@ static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret)
if (s->packet_transfer_size <= 0) {
s->status = READY_STAT | SEEK_STAT;
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
goto eot;
}

4
hw/ide/cmd646.c
View File

@ -294,11 +294,11 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
qdev_init_gpio_in(ds, cmd646_set_irq, 2);
for (i = 0; i < 2; i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_register_restart_cb(&d->bus[i]);
ide_bus_register_restart_cb(&d->bus[i]);
}
}

80
hw/ide/core.c
View File

@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/isa/isa.h"
#include "migration/vmstate.h"
#include "qemu/error-report.h"
@ -653,7 +654,7 @@ void ide_set_sector(IDEState *s, int64_t sector_num)
static void ide_rw_error(IDEState *s) {
ide_abort_command(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_buffered_readv_cb(void *opaque, int ret)
@ -772,7 +773,7 @@ static void ide_sector_read_cb(void *opaque, int ret)
s->nsector -= n;
/* Allow the guest to read the io_buffer */
ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_sector_read(IDEState *s)
@ -836,7 +837,7 @@ void ide_dma_error(IDEState *s)
dma_buf_commit(s, 0);
ide_abort_command(s);
ide_set_inactive(s, false);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
int ide_handle_rw_error(IDEState *s, int error, int op)
@ -906,7 +907,7 @@ static void ide_dma_cb(void *opaque, int ret)
/* end of transfer ? */
if (s->nsector == 0) {
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
goto eot;
}
@ -1006,7 +1007,7 @@ static void ide_sector_write(IDEState *s);
static void ide_sector_write_timer_cb(void *opaque)
{
IDEState *s = opaque;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_sector_write_cb(void *opaque, int ret)
@ -1054,7 +1055,7 @@ static void ide_sector_write_cb(void *opaque, int ret)
timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(NANOSECONDS_PER_SECOND / 1000));
} else {
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
}
@ -1105,7 +1106,7 @@ static void ide_flush_cb(void *opaque, int ret)
}
s->status = READY_STAT | SEEK_STAT;
ide_cmd_done(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_flush_cache(IDEState *s)
@ -1194,7 +1195,7 @@ static void ide_cd_change_cb(void *opaque, bool load, Error **errp)
s->cdrom_changed = 1;
s->events.new_media = true;
s->events.eject_request = false;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_cd_eject_request_cb(void *opaque, bool force)
@ -1205,7 +1206,7 @@ static void ide_cd_eject_request_cb(void *opaque, bool force)
if (force) {
s->tray_locked = false;
}
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_cmd_lba48_transform(IDEState *s, int lba48)
@ -1264,7 +1265,7 @@ const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] = {
void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
int reg_num = addr & 7;
trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);
@ -1326,7 +1327,7 @@ void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
case ATA_IOPORT_WR_COMMAND:
ide_clear_hob(bus);
qemu_irq_lower(bus->irq);
ide_exec_cmd(bus, val);
ide_bus_exec_cmd(bus, val);
break;
}
}
@ -1439,7 +1440,7 @@ static bool cmd_identify(IDEState *s, uint8_t cmd)
}
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
} else {
if (s->drive_kind == IDE_CD) {
@ -1629,7 +1630,7 @@ static bool cmd_specify(IDEState *s, uint8_t cmd)
if (s->blk && s->drive_kind != IDE_CD) {
s->heads = (s->select & (ATA_DEV_HS)) + 1;
s->sectors = s->nsector;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
} else {
ide_abort_command(s);
}
@ -1730,7 +1731,7 @@ static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
ide_atapi_identify(s);
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
}
@ -1755,7 +1756,7 @@ static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
* They are part of the regular output (this is why ERR_STAT isn't set)
* Device 0 passed, Device 1 passed or not present. */
s->error = 0x01;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
return false;
@ -1787,7 +1788,7 @@ static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
{
s->error = 0x09; /* miscellaneous error */
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
}
@ -1826,7 +1827,7 @@ static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
s->io_buffer[0x1a] = 0x01; /* Hot count */
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
}
@ -1850,7 +1851,7 @@ static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
s->status = 0x00; /* NOTE: READY is _not_ set */
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
}
@ -1933,7 +1934,7 @@ static bool cmd_smart(IDEState *s, uint8_t cmd)
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
case SMART_READ_DATA:
@ -1974,7 +1975,7 @@ static bool cmd_smart(IDEState *s, uint8_t cmd)
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
case SMART_READ_LOG:
@ -2013,7 +2014,7 @@ static bool cmd_smart(IDEState *s, uint8_t cmd)
}
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
case SMART_EXECUTE_OFFLINE:
@ -2122,13 +2123,13 @@ static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
&& (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
}
void ide_exec_cmd(IDEBus *bus, uint32_t val)
void ide_bus_exec_cmd(IDEBus *bus, uint32_t val)
{
IDEState *s;
bool complete;
s = idebus_active_if(bus);
trace_ide_exec_cmd(bus, s, val);
s = ide_bus_active_if(bus);
trace_ide_bus_exec_cmd(bus, s, val);
/* ignore commands to non existent slave */
if (s != bus->ifs && !s->blk) {
@ -2145,7 +2146,7 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
if (!ide_cmd_permitted(s, val)) {
ide_abort_command(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return;
}
@ -2163,7 +2164,7 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
}
ide_cmd_done(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
}
@ -2194,7 +2195,7 @@ const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] = {
uint32_t ide_ioport_read(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint32_t reg_num;
int ret, hob;
@ -2280,7 +2281,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
uint32_t ide_status_read(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
int ret;
if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
@ -2369,7 +2370,7 @@ static bool ide_is_pio_out(IDEState *s)
void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
trace_ide_data_writew(addr, val, bus, s);
@ -2405,7 +2406,7 @@ void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
uint32_t ide_data_readw(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
int ret;
@ -2443,7 +2444,7 @@ uint32_t ide_data_readw(void *opaque, uint32_t addr)
void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
trace_ide_data_writel(addr, val, bus, s);
@ -2471,7 +2472,7 @@ void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
uint32_t ide_data_readl(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
int ret;
@ -2710,7 +2711,7 @@ static void ide_restart_bh(void *opaque)
return;
}
s = idebus_active_if(bus);
s = ide_bus_active_if(bus);
is_read = (bus->error_status & IDE_RETRY_READ) != 0;
/* The error status must be cleared before resubmitting the request: The
@ -2758,7 +2759,7 @@ static void ide_restart_cb(void *opaque, bool running, RunState state)
}
}
void ide_register_restart_cb(IDEBus *bus)
void ide_bus_register_restart_cb(IDEBus *bus)
{
if (bus->dma->ops->restart_dma) {
bus->vmstate = qemu_add_vm_change_state_handler(ide_restart_cb, bus);
@ -2770,7 +2771,7 @@ static IDEDMA ide_dma_nop = {
.aiocb = NULL,
};
void ide_init2(IDEBus *bus, qemu_irq irq)
void ide_bus_init_output_irq(IDEBus *bus, qemu_irq irq_out)
{
int i;
@ -2778,10 +2779,17 @@ void ide_init2(IDEBus *bus, qemu_irq irq)
ide_init1(bus, i);
ide_reset(&bus->ifs[i]);
}
bus->irq = irq;
bus->irq = irq_out;
bus->dma = &ide_dma_nop;
}
void ide_bus_set_irq(IDEBus *bus)
{
if (!(bus->cmd & IDE_CTRL_DISABLE_IRQ)) {
qemu_irq_raise(bus->irq);
}
}
void ide_exit(IDEState *s)
{
timer_free(s->sector_write_timer);

1
hw/ide/ich.c
View File

@ -61,6 +61,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/msi.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"

10
hw/ide/ioport.c
View File

@ -25,16 +25,6 @@
#include "qemu/osdep.h"
#include "hw/isa/isa.h"
#include "qemu/error-report.h"
#include "qemu/timer.h"
#include "sysemu/blockdev.h"
#include "sysemu/dma.h"
#include "hw/block/block.h"
#include "sysemu/block-backend.h"
#include "qapi/error.h"
#include "qemu/cutils.h"
#include "sysemu/replay.h"
#include "hw/ide/internal.h"
#include "trace.h"

22
hw/ide/isa.c
View File

@ -31,23 +31,20 @@
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "hw/ide/isa.h"
#include "hw/ide/internal.h"
#include "qom/object.h"
/***********************************************************/
/* ISA IDE definitions */
#define TYPE_ISA_IDE "isa-ide"
OBJECT_DECLARE_SIMPLE_TYPE(ISAIDEState, ISA_IDE)
struct ISAIDEState {
ISADevice parent_obj;
IDEBus bus;
uint32_t iobase;
uint32_t iobase2;
uint32_t isairq;
qemu_irq irq;
uint32_t irqnum;
};
static void isa_ide_reset(DeviceState *d)
@ -75,13 +72,12 @@ static void isa_ide_realizefn(DeviceState *dev, Error **errp)
ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2);
ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2);
s->irq = isa_get_irq(isadev, s->isairq);
ide_init2(&s->bus, s->irq);
ide_bus_init_output_irq(&s->bus, isa_get_irq(isadev, s->irqnum));
vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_isa, s);
ide_register_restart_cb(&s->bus);
ide_bus_register_restart_cb(&s->bus);
}
ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int irqnum,
DriveInfo *hd0, DriveInfo *hd1)
{
DeviceState *dev;
@ -92,15 +88,15 @@ ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "iobase", iobase);
qdev_prop_set_uint32(dev, "iobase2", iobase2);
qdev_prop_set_uint32(dev, "irq", isairq);
qdev_prop_set_uint32(dev, "irq", irqnum);
isa_realize_and_unref(isadev, bus, &error_fatal);
s = ISA_IDE(dev);
if (hd0) {
ide_create_drive(&s->bus, 0, hd0);
ide_bus_create_drive(&s->bus, 0, hd0);
}
if (hd1) {
ide_create_drive(&s->bus, 1, hd1);
ide_bus_create_drive(&s->bus, 1, hd1);
}
return isadev;
}
@ -108,7 +104,7 @@ ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
static Property isa_ide_properties[] = {
DEFINE_PROP_UINT32("iobase", ISAIDEState, iobase, 0x1f0),
DEFINE_PROP_UINT32("iobase2", ISAIDEState, iobase2, 0x3f6),
DEFINE_PROP_UINT32("irq", ISAIDEState, isairq, 14),
DEFINE_PROP_UINT32("irq", ISAIDEState, irqnum, 14),
DEFINE_PROP_END_OF_LIST(),
};

15
hw/ide/macio.c
View File

@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/ppc/mac_dbdma.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
@ -59,7 +60,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);
int64_t offset;
MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
@ -135,7 +136,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);
int64_t offset;
MACIO_DPRINTF("pmac_ide_transfer_cb\n");
@ -159,7 +160,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
MACIO_DPRINTF("End of IDE transfer\n");
qemu_sglist_destroy(&s->sg);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
m->dma_active = false;
goto done;
}
@ -219,7 +220,7 @@ done:
static void pmac_ide_transfer(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);
MACIO_DPRINTF("\n");
@ -250,7 +251,7 @@ static void pmac_ide_transfer(DBDMA_io *io)
static void pmac_ide_flush(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);
if (s->bus->dma->aiocb) {
blk_drain(s->blk);
@ -419,7 +420,7 @@ static void macio_ide_realizefn(DeviceState *dev, Error **errp)
{
MACIOIDEState *s = MACIO_IDE(dev);
ide_init2(&s->bus, s->ide_irq);
ide_bus_init_output_irq(&s->bus, s->ide_irq);
/* Register DMA callbacks */
s->dma.ops = &dbdma_ops;
@ -500,7 +501,7 @@ void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
for (i = 0; i < 2; i++) {
if (hd_table[i]) {
ide_create_drive(&s->bus, i, hd_table[i]);
ide_bus_create_drive(&s->bus, i, hd_table[i]);
}
}
}

9
hw/ide/microdrive.c
View File

@ -29,6 +29,7 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "hw/irq.h"
#include "hw/ide/internal.h"
#include "qom/object.h"
@ -249,14 +250,14 @@ static uint16_t md_common_read(PCMCIACardState *card, uint32_t at)
case 0xd: /* Error */
return ide_ioport_read(&s->bus, 0x1);
case 0xe: /* Alternate Status */
ifs = idebus_active_if(&s->bus);
ifs = ide_bus_active_if(&s->bus);
if (ifs->blk) {
return ifs->status;
} else {
return 0;
}
case 0xf: /* Device Address */
ifs = idebus_active_if(&s->bus);
ifs = ide_bus_active_if(&s->bus);
return 0xc2 | ((~ifs->select << 2) & 0x3c);
default:
return ide_ioport_read(&s->bus, at);
@ -565,7 +566,7 @@ PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo)
qdev_realize(DEVICE(md), NULL, &error_fatal);
if (dinfo != NULL) {
ide_create_drive(&md->bus, 0, dinfo);
ide_bus_create_drive(&md->bus, 0, dinfo);
}
md->bus.ifs[0].drive_kind = IDE_CFATA;
md->bus.ifs[0].mdata_size = METADATA_SIZE;
@ -598,7 +599,7 @@ static void microdrive_realize(DeviceState *dev, Error **errp)
{
MicroDriveState *md = MICRODRIVE(dev);
ide_init2(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
ide_bus_init_output_irq(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
}
static void microdrive_init(Object *obj)

37
hw/ide/mmio.c
View File

@ -29,9 +29,9 @@
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "hw/ide/mmio.h"
#include "hw/ide/internal.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
/***********************************************************/
/* MMIO based ide port
@ -39,11 +39,6 @@
* dedicated ide controller, which is often seen on embedded boards.
*/
#define TYPE_MMIO_IDE "mmio-ide"
typedef struct MMIOIDEState MMIOState;
DECLARE_INSTANCE_CHECKER(MMIOState, MMIO_IDE,
TYPE_MMIO_IDE)
struct MMIOIDEState {
/*< private >*/
SysBusDevice parent_obj;
@ -58,7 +53,7 @@ struct MMIOIDEState {
static void mmio_ide_reset(DeviceState *dev)
{
MMIOState *s = MMIO_IDE(dev);
MMIOIDEState *s = MMIO_IDE(dev);
ide_bus_reset(&s->bus);
}
@ -66,7 +61,7 @@ static void mmio_ide_reset(DeviceState *dev)
static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s = opaque;
MMIOIDEState *s = opaque;
addr >>= s->shift;
if (addr & 7)
return ide_ioport_read(&s->bus, addr);
@ -77,7 +72,7 @@ static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
static void mmio_ide_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
MMIOIDEState *s = opaque;
addr >>= s->shift;
if (addr & 7)
ide_ioport_write(&s->bus, addr, val);
@ -94,14 +89,14 @@ static const MemoryRegionOps mmio_ide_ops = {
static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s= opaque;
MMIOIDEState *s = opaque;
return ide_status_read(&s->bus, 0);
}
static void mmio_ide_ctrl_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
MMIOIDEState *s = opaque;
ide_ctrl_write(&s->bus, 0, val);
}
@ -116,8 +111,8 @@ static const VMStateDescription vmstate_ide_mmio = {
.version_id = 3,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_IDE_BUS(bus, MMIOState),
VMSTATE_IDE_DRIVES(bus.ifs, MMIOState),
VMSTATE_IDE_BUS(bus, MMIOIDEState),
VMSTATE_IDE_DRIVES(bus.ifs, MMIOIDEState),
VMSTATE_END_OF_LIST()
}
};
@ -125,9 +120,9 @@ static const VMStateDescription vmstate_ide_mmio = {
static void mmio_ide_realizefn(DeviceState *dev, Error **errp)
{
SysBusDevice *d = SYS_BUS_DEVICE(dev);
MMIOState *s = MMIO_IDE(dev);
MMIOIDEState *s = MMIO_IDE(dev);
ide_init2(&s->bus, s->irq);
ide_bus_init_output_irq(&s->bus, s->irq);
memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s,
"ide-mmio.1", 16 << s->shift);
@ -140,14 +135,14 @@ static void mmio_ide_realizefn(DeviceState *dev, Error **errp)
static void mmio_ide_initfn(Object *obj)
{
SysBusDevice *d = SYS_BUS_DEVICE(obj);
MMIOState *s = MMIO_IDE(obj);
MMIOIDEState *s = MMIO_IDE(obj);
ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
sysbus_init_irq(d, &s->irq);
}
static Property mmio_ide_properties[] = {
DEFINE_PROP_UINT32("shift", MMIOState, shift, 0),
DEFINE_PROP_UINT32("shift", MMIOIDEState, shift, 0),
DEFINE_PROP_END_OF_LIST()
};
@ -164,7 +159,7 @@ static void mmio_ide_class_init(ObjectClass *oc, void *data)
static const TypeInfo mmio_ide_type_info = {
.name = TYPE_MMIO_IDE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MMIOState),
.instance_size = sizeof(MMIOIDEState),
.instance_init = mmio_ide_initfn,
.class_init = mmio_ide_class_init,
};
@ -176,13 +171,13 @@ static void mmio_ide_register_types(void)
void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1)
{
MMIOState *s = MMIO_IDE(dev);
MMIOIDEState *s = MMIO_IDE(dev);
if (hd0 != NULL) {
ide_create_drive(&s->bus, 0, hd0);
ide_bus_create_drive(&s->bus, 0, hd0);
}
if (hd1 != NULL) {
ide_create_drive(&s->bus, 1, hd1);
ide_bus_create_drive(&s->bus, 1, hd1);
}
}

11
hw/ide/pci.c
View File

@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "sysemu/dma.h"
@ -103,6 +104,12 @@ const MemoryRegionOps pci_ide_data_le_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static IDEState *bmdma_active_if(BMDMAState *bmdma)
{
assert(bmdma->bus->retry_unit != (uint8_t)-1);
return bmdma->bus->ifs + bmdma->bus->retry_unit;
}
static void bmdma_start_dma(const IDEDMA *dma, IDEState *s,
BlockCompletionFunc *dma_cb)
{
@ -295,7 +302,7 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
/* Ignore writes to SSBM if it keeps the old value */
if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
if (!(val & BM_CMD_START)) {
ide_cancel_dma_sync(idebus_active_if(bm->bus));
ide_cancel_dma_sync(ide_bus_active_if(bm->bus));
bm->status &= ~BM_STATUS_DMAING;
} else {
bm->cur_addr = bm->addr;
@ -488,7 +495,7 @@ void pci_ide_create_devs(PCIDevice *dev)
ide_drive_get(hd_table, ARRAY_SIZE(hd_table));
for (i = 0; i < 4; i++) {
if (hd_table[i]) {
ide_create_drive(d->bus + bus[i], unit[i], hd_table[i]);
ide_bus_create_drive(d->bus + bus[i], unit[i], hd_table[i]);
}
}
}

46
hw/ide/piix.c
View File

@ -28,14 +28,9 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "sysemu/dma.h"
#include "hw/pci/pci.h"
#include "hw/ide/piix.h"
#include "hw/ide/pci.h"
#include "trace.h"
@ -126,7 +121,7 @@ static void piix_ide_reset(DeviceState *dev)
pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */
}
static int pci_piix_init_ports(PCIIDEState *d)
static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)
{
static const struct {
int iobase;
@ -136,30 +131,29 @@ static int pci_piix_init_ports(PCIIDEState *d)
{0x1f0, 0x3f6, 14},
{0x170, 0x376, 15},
};
int i, ret;
int ret;
for (i = 0; i < 2; i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
port_info[i].iobase2);
if (ret) {
return ret;
}
ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_register_restart_cb(&d->bus[i]);
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
port_info[i].iobase2);
if (ret) {
error_setg_errno(errp, -ret, "Failed to realize %s port %u",
object_get_typename(OBJECT(d)), i);
return false;
}
ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
return 0;
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_bus_register_restart_cb(&d->bus[i]);
return true;
}
static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
int rc;
pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
@ -168,10 +162,10 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d);
rc = pci_piix_init_ports(d);
if (rc) {
error_setg_errno(errp, -rc, "Failed to realize %s",
object_get_typename(OBJECT(dev)));
for (unsigned i = 0; i < 2; i++) {
if (!pci_piix_init_bus(d, i, errp)) {
return;
}
}
}

2
hw/ide/qdev.c
View File

@ -124,7 +124,7 @@ static void ide_qdev_realize(DeviceState *qdev, Error **errp)
dc->realize(dev, errp);
}
IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive)
IDEDevice *ide_bus_create_drive(IDEBus *bus, int unit, DriveInfo *drive)
{
DeviceState *dev;

4
hw/ide/sii3112.c
View File

@ -284,11 +284,11 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
qdev_init_gpio_in(ds, sii3112_set_irq, 2);
for (i = 0; i < 2; i++) {
ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
ide_init2(&s->bus[i], qdev_get_gpio_in(ds, i));
ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&s->bus[i], &s->bmdma[i], s);
s->bmdma[i].bus = &s->bus[i];
ide_register_restart_cb(&s->bus[i]);
ide_bus_register_restart_cb(&s->bus[i]);
}
}

3
hw/ide/trace-events
View File

@ -12,7 +12,7 @@ ide_data_writew(uint32_t addr, uint32_t val, void *bus, void *s)
ide_data_readl(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p; IDEState %p"
ide_data_writel(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO wr @ 0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p; IDEState %p"
# misc
ide_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; state %p; cmd 0x%02x"
ide_bus_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; state %p; cmd 0x%02x"
ide_cancel_dma_sync_buffered(void *fn, void *req) "invoking cb %p of buffered request %p with -ECANCELED"
ide_cancel_dma_sync_remaining(void) "draining all remaining requests"
ide_sector_read(int64_t sector_num, int nsectors) "sector=%"PRId64" nsectors=%d"
@ -91,6 +91,7 @@ ahci_populate_sglist_short_map(void *s, int port) "ahci(%p)[%d]: mapped less tha
ahci_populate_sglist_bad_offset(void *s, int port, int off_idx, int64_t off_pos) "ahci(%p)[%d]: Incorrect offset! off_idx: %d, off_pos: %"PRId64
ncq_finish(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:%d]: NCQ transfer finished"
execute_ncq_command_read(void *s, int port, uint8_t tag, int count, int64_t lba) "ahci(%p)[%d][tag:%d]: NCQ reading %d sectors from LBA %"PRId64
execute_ncq_command_write(void *s, int port, uint8_t tag, int count, int64_t lba) "ahci(%p)[%d][tag:%d]: NCQ writing %d sectors to LBA %"PRId64
execute_ncq_command_unsup(void *s, int port, uint8_t tag, uint8_t cmd) "ahci(%p)[%d][tag:%d]: error: unsupported NCQ command (0x%02x) received"
process_ncq_command_mismatch(void *s, int port, uint8_t tag, uint8_t slot) "ahci(%p)[%d][tag:%d]: Warning: NCQ slot (%d) did not match the given tag"
process_ncq_command_aux(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:%d]: Warn: Attempt to use NCQ auxiliary fields"

16
hw/ide/via.c
View File

@ -90,7 +90,7 @@ static void bmdma_setup_bar(PCIIDEState *d)
int i;
memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
for(i = 0;i < 2; i++) {
for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) {
BMDMAState *bm = &d->bmdma[i];
memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
@ -122,7 +122,7 @@ static void via_ide_reset(DeviceState *dev)
uint8_t *pci_conf = pd->config;
int i;
for (i = 0; i < 2; i++) {
for (i = 0; i < ARRAY_SIZE(d->bus); i++) {
ide_bus_reset(&d->bus[i]);
}
@ -188,14 +188,14 @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
bmdma_setup_bar(d);
pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
qdev_init_gpio_in(ds, via_ide_set_irq, 2);
for (i = 0; i < 2; i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
qdev_init_gpio_in(ds, via_ide_set_irq, ARRAY_SIZE(d->bus));
for (i = 0; i < ARRAY_SIZE(d->bus); i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, MAX_IDE_DEVS);
ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_register_restart_cb(&d->bus[i]);
ide_bus_register_restart_cb(&d->bus[i]);
}
}
@ -204,7 +204,7 @@ static void via_ide_exitfn(PCIDevice *dev)
PCIIDEState *d = PCI_IDE(dev);
unsigned i;
for (i = 0; i < 2; ++i) {
for (i = 0; i < ARRAY_SIZE(d->bmdma); ++i) {
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
}

2
hw/intc/apic.c
View File

@ -20,7 +20,7 @@
#include "qemu/thread.h"
#include "hw/i386/apic_internal.h"
#include "hw/i386/apic.h"
#include "hw/i386/ioapic.h"
#include "hw/intc/ioapic.h"
#include "hw/intc/i8259.h"
#include "hw/intc/kvm_irqcount.h"
#include "hw/pci/msi.h"

4
hw/intc/i8259.c
View File

@ -406,7 +406,7 @@ static void pic_realize(DeviceState *dev, Error **errp)
pc->parent_realize(dev, errp);
}
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in)
{
qemu_irq *irq_set;
DeviceState *dev;
@ -418,7 +418,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
isadev = i8259_init_chip(TYPE_I8259, bus, true);
dev = DEVICE(isadev);
qdev_connect_gpio_out(dev, 0, parent_irq);
qdev_connect_gpio_out(dev, 0, parent_irq_in);
for (i = 0 ; i < 8; i++) {
irq_set[i] = qdev_get_gpio_in(dev, i);
}

4
hw/intc/ioapic.c
View File

@ -24,10 +24,10 @@
#include "qapi/error.h"
#include "monitor/monitor.h"
#include "hw/i386/apic.h"
#include "hw/i386/ioapic.h"
#include "hw/i386/ioapic_internal.h"
#include "hw/i386/x86.h"
#include "hw/intc/i8259.h"
#include "hw/intc/ioapic.h"
#include "hw/intc/ioapic_internal.h"
#include "hw/pci/msi.h"
#include "hw/qdev-properties.h"
#include "sysemu/kvm.h"

4
hw/intc/ioapic_common.c
View File

@ -24,9 +24,9 @@
#include "qemu/module.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/i386/ioapic.h"
#include "hw/i386/ioapic_internal.h"
#include "hw/intc/intc.h"
#include "hw/intc/ioapic.h"
#include "hw/intc/ioapic_internal.h"
#include "hw/sysbus.h"
/* ioapic_no count start from 0 to MAX_IOAPICS,

8
include/hw/i386/ioapic_internal.h → hw/intc/ioapic_internal.h
View File

@ -19,11 +19,11 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef QEMU_IOAPIC_INTERNAL_H
#define QEMU_IOAPIC_INTERNAL_H
#ifndef HW_INTC_IOAPIC_INTERNAL_H
#define HW_INTC_IOAPIC_INTERNAL_H
#include "exec/memory.h"
#include "hw/i386/ioapic.h"
#include "hw/intc/ioapic.h"
#include "hw/sysbus.h"
#include "qemu/notify.h"
#include "qom/object.h"
@ -115,4 +115,4 @@ void ioapic_reset_common(DeviceState *dev);
void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level);
#endif /* QEMU_IOAPIC_INTERNAL_H */
#endif /* HW_INTC_IOAPIC_INTERNAL_H */

19
hw/isa/i82378.c
View File

@ -32,8 +32,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(I82378State, I82378)
struct I82378State {
PCIDevice parent_obj;
qemu_irq out[2];
qemu_irq *i8259;
qemu_irq cpu_intr;
qemu_irq *isa_irqs_in;
MemoryRegion io;
};
@ -47,18 +47,12 @@ static const VMStateDescription vmstate_i82378 = {
},
};
static void i82378_request_out0_irq(void *opaque, int irq, int level)
{
I82378State *s = opaque;
qemu_set_irq(s->out[0], level);
}
static void i82378_request_pic_irq(void *opaque, int irq, int level)
{
DeviceState *dev = opaque;
I82378State *s = I82378(dev);
qemu_set_irq(s->i8259[irq], level);
qemu_set_irq(s->isa_irqs_in[irq], level);
}
static void i82378_realize(PCIDevice *pci, Error **errp)
@ -94,9 +88,8 @@ static void i82378_realize(PCIDevice *pci, Error **errp)
*/
/* 2 82C59 (irq) */
s->i8259 = i8259_init(isabus,
qemu_allocate_irq(i82378_request_out0_irq, s, 0));
isa_bus_irqs(isabus, s->i8259);
s->isa_irqs_in = i8259_init(isabus, s->cpu_intr);
isa_bus_register_input_irqs(isabus, s->isa_irqs_in);
/* 1 82C54 (pit) */
pit = i8254_pit_init(isabus, 0x40, 0, NULL);
@ -113,7 +106,7 @@ static void i82378_init(Object *obj)
DeviceState *dev = DEVICE(obj);
I82378State *s = I82378(obj);
qdev_init_gpio_out(dev, s->out, 1);
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);
}

32
hw/isa/isa-bus.c
View File

@ -67,13 +67,20 @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space,
return isabus;
}
void isa_bus_irqs(ISABus *bus, qemu_irq *irqs)
void isa_bus_register_input_irqs(ISABus *bus, qemu_irq *irqs_in)
{
bus->irqs = irqs;
bus->irqs_in = irqs_in;
}
qemu_irq isa_bus_get_irq(ISABus *bus, unsigned irqnum)
{
assert(irqnum < ISA_NUM_IRQS);
assert(bus->irqs_in);
return bus->irqs_in[irqnum];
}
/*
* isa_get_irq() returns the corresponding qemu_irq entry for the i8259.
* isa_get_irq() returns the corresponding input qemu_irq entry for the i8259.
*
* This function is only for special cases such as the 'ferr', and
* temporary use for normal devices until they are converted to qdev.
@ -81,14 +88,13 @@ void isa_bus_irqs(ISABus *bus, qemu_irq *irqs)
qemu_irq isa_get_irq(ISADevice *dev, unsigned isairq)
{
assert(!dev || ISA_BUS(qdev_get_parent_bus(DEVICE(dev))) == isabus);
assert(isairq < ISA_NUM_IRQS);
return isabus->irqs[isairq];
return isa_bus_get_irq(isabus, isairq);
}
void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, unsigned isairq)
{
qemu_irq irq = isa_get_irq(isadev, isairq);
qdev_connect_gpio_out(DEVICE(isadev), gpioirq, irq);
qemu_irq input_irq = isa_get_irq(isadev, isairq);
qdev_connect_gpio_out(DEVICE(isadev), gpioirq, input_irq);
}
void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16)
@ -99,7 +105,7 @@ void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16)
bus->dma[1] = dma16;
}
IsaDma *isa_get_dma(ISABus *bus, int nchan)
IsaDma *isa_bus_get_dma(ISABus *bus, int nchan)
{
assert(bus);
return bus->dma[nchan > 3 ? 1 : 0];
@ -114,7 +120,7 @@ static inline void isa_init_ioport(ISADevice *dev, uint16_t ioport)
void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start)
{
memory_region_add_subregion(isabus->address_space_io, start, io);
memory_region_add_subregion(isa_address_space_io(dev), start, io);
isa_init_ioport(dev, start);
}
@ -135,7 +141,7 @@ int isa_register_portio_list(ISADevice *dev,
isa_init_ioport(dev, start);
portio_list_init(piolist, OBJECT(dev), pio_start, opaque, name);
portio_list_add(piolist, isabus->address_space_io, start);
portio_list_add(piolist, isa_address_space_io(dev), start);
return 0;
}
@ -164,6 +170,11 @@ bool isa_realize_and_unref(ISADevice *dev, ISABus *bus, Error **errp)
return qdev_realize_and_unref(&dev->parent_obj, &bus->parent_obj, errp);
}
ISABus *isa_bus_from_device(ISADevice *dev)
{
return ISA_BUS(qdev_get_parent_bus(DEVICE(dev)));
}
ISADevice *isa_vga_init(ISABus *bus)
{
vga_interface_created = true;
@ -213,7 +224,6 @@ static const TypeInfo isa_device_type_info = {
.parent = TYPE_DEVICE,
.instance_size = sizeof(ISADevice),
.abstract = true,
.class_size = sizeof(ISADeviceClass),
.class_init = isa_device_class_init,
};

36
hw/isa/lpc_ich9.c
View File

@ -40,8 +40,8 @@
#include "hw/irq.h"
#include "hw/isa/apm.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
#include "hw/i386/pc.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"
@ -57,8 +57,6 @@
/*****************************************************************************/
/* ICH9 LPC PCI to ISA bridge */
static void ich9_lpc_reset(DeviceState *qdev);
/* chipset configuration register
* to access chipset configuration registers, pci_[sg]et_{byte, word, long}
* are used.
@ -259,7 +257,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
qemu_set_irq(lpc->gsi[gsi], level);
}
void ich9_lpc_set_irq(void *opaque, int pirq, int level)
static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
{
ICH9LPCState *lpc = opaque;
int pic_irq, pic_dis;
@ -275,7 +273,7 @@ void ich9_lpc_set_irq(void *opaque, int pirq, int level)
/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
* a given device irq pin.
*/
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
{
BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
PCIBus *pci_bus = PCI_BUS(bus);
@ -286,7 +284,7 @@ int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
}
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
{
ICH9LPCState *lpc = opaque;
PCIINTxRoute route;
@ -407,14 +405,13 @@ static void smi_features_ok_callback(void *opaque)
lpc->smi_features_ok = 1;
}
void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
static void ich9_lpc_pm_init(ICH9LPCState *lpc)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
qemu_irq sci_irq;
FWCfgState *fw_cfg = fw_cfg_find();
sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
ich9_pm_init(PCI_DEVICE(lpc), &lpc->pm, sci_irq);
if (lpc->smi_host_features && fw_cfg) {
uint64_t host_features_le;
@ -440,8 +437,6 @@ void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
sizeof lpc->smi_features_ok,
true);
}
ich9_lpc_reset(DEVICE(lpc));
}
/* APM */
@ -680,6 +675,7 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
DeviceState *dev = DEVICE(d);
PCIBus *pci_bus = pci_get_bus(d);
ISABus *isa_bus;
if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) &&
@ -709,8 +705,6 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc,
"lpc-rcrb-mmio", ICH9_CC_SIZE);
lpc->isa_bus = isa_bus;
ich9_cc_init(lpc);
apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);
@ -723,11 +717,17 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
1);
qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, IOAPIC_NUM_PINS);
isa_bus_irqs(isa_bus, lpc->gsi);
isa_bus_register_input_irqs(isa_bus, lpc->gsi);
i8257_dma_init(isa_bus, 0);
pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS);
pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq);
pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq);
ich9_lpc_pm_init(lpc);
}
static bool ich9_rst_cnt_needed(void *opaque)
@ -794,6 +794,7 @@ static const VMStateDescription vmstate_ich9_lpc = {
static Property ich9_lpc_properties[] = {
DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, false),
DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false),
DEFINE_PROP_BOOL("smm-enabled", ICH9LPCState, pm.smm_enabled, false),
DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
ICH9_LPC_SMI_F_BROADCAST_BIT, true),
DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features,
@ -813,8 +814,7 @@ static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
{
Aml *field;
ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
BusState *bus = BUS(s->isa_bus);
BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
Aml *sb_scope = aml_scope("\\_SB");
/* ICH9 PCI to ISA irq remapping */

4
hw/isa/piix4.c
View File

@ -47,7 +47,7 @@ struct PIIX4State {
qemu_irq cpu_intr;
qemu_irq *isa;
RTCState rtc;
MC146818RtcState rtc;
PCIIDEState ide;
UHCIState uhci;
PIIX4PMState pm;
@ -212,7 +212,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
s->isa = i8259_init(isa_bus, *i8259_out_irq);
/* initialize ISA irqs */
isa_bus_irqs(isa_bus, s->isa);
isa_bus_register_input_irqs(isa_bus, s->isa);
/* initialize pit */
i8254_pit_init(isa_bus, 0x40, 0, NULL);

18
hw/isa/vt82c686.c
View File

@ -548,9 +548,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA)
struct ViaISAState {
PCIDevice dev;
qemu_irq cpu_intr;
qemu_irq *isa_irqs;
qemu_irq *isa_irqs_in;
ViaSuperIOState via_sio;
RTCState rtc;
MC146818RtcState rtc;
PCIIDEState ide;
UHCIState uhci[2];
ViaPMState pm;
@ -595,13 +595,7 @@ static const TypeInfo via_isa_info = {
void via_isa_set_irq(PCIDevice *d, int n, int level)
{
ViaISAState *s = VIA_ISA(d);
qemu_set_irq(s->isa_irqs[n], level);
}
static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
{
ViaISAState *s = opaque;
qemu_set_irq(s->cpu_intr, level);
qemu_set_irq(s->isa_irqs_in[n], level);
}
static void via_isa_realize(PCIDevice *d, Error **errp)
@ -609,12 +603,10 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
ViaISAState *s = VIA_ISA(d);
DeviceState *dev = DEVICE(d);
PCIBus *pci_bus = pci_get_bus(d);
qemu_irq *isa_irq;
ISABus *isa_bus;
int i;
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);
isa_bus = isa_bus_new(dev, pci_address_space(d), pci_address_space_io(d),
errp);
@ -622,8 +614,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
return;
}
s->isa_irqs = i8259_init(isa_bus, *isa_irq);
isa_bus_irqs(isa_bus, s->isa_irqs);
s->isa_irqs_in = i8259_init(isa_bus, s->cpu_intr);
isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
i8254_pit_init(isa_bus, 0x40, 0, NULL);
i8257_dma_init(isa_bus, 0);

2
hw/mips/jazz.c
View File

@ -249,7 +249,7 @@ static void mips_jazz_init(MachineState *machine,
/* ISA devices */
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
isa_bus_register_input_irqs(isa_bus, i8259);
i8257_dma_init(isa_bus, 0);
pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit);

1
hw/misc/macio/gpio.c
View File

@ -28,6 +28,7 @@
#include "migration/vmstate.h"
#include "hw/misc/macio/macio.h"
#include "hw/misc/macio/gpio.h"
#include "hw/irq.h"
#include "hw/nmi.h"
#include "qemu/log.h"
#include "qemu/module.h"

1
hw/nubus/nubus-device.c
View File

@ -80,6 +80,7 @@ static void nubus_device_realize(DeviceState *dev, Error **errp)
&error_abort);
ret = load_image_mr(path, &nd->decl_rom);
g_free(path);
g_free(name);
if (ret < 0) {
error_setg(errp, "could not load romfile \"%s\"", nd->romfile);
return;

2
hw/pci-bridge/i82801b11.c
View File

@ -45,7 +45,7 @@
#include "hw/pci/pci_bridge.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
/*****************************************************************************/
/* ICH9 DMI-to-PCI bridge */

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