mirror of https://github.com/proxmox/mirror_qemu
tcg/ppc: Support 128-bit load/store
Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required. Note that these instructions do not require 16-byte alignment. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>master
Richard Henderson
parent
929124ec0b
commit
526cd4ec01
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@ -14,6 +14,7 @@ C_O0_I2(r, r)
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C_O0_I2(r, ri)
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C_O0_I2(v, r)
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C_O0_I3(r, r, r)
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C_O0_I3(o, m, r)
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C_O0_I4(r, r, ri, ri)
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C_O0_I4(r, r, r, r)
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C_O1_I1(r, r)
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@ -34,6 +35,7 @@ C_O1_I3(v, v, v, v)
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C_O1_I4(r, r, ri, rZ, rZ)
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C_O1_I4(r, r, r, ri, ri)
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C_O2_I1(r, r, r)
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C_O2_I1(o, m, r)
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C_O2_I2(r, r, r, r)
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C_O2_I4(r, r, rI, rZM, r, r)
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C_O2_I4(r, r, r, r, rI, rZM)
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@ -9,6 +9,7 @@
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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REGS('o', ALL_GENERAL_REGS & 0xAAAAAAAAu) /* odd registers */
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REGS('v', ALL_VECTOR_REGS)
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/*
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@ -295,25 +295,27 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
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#define B OPCD( 18)
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#define BC OPCD( 16)
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#define LBZ OPCD( 34)
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#define LHZ OPCD( 40)
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#define LHA OPCD( 42)
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#define LWZ OPCD( 32)
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#define LWZUX XO31( 55)
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#define STB OPCD( 38)
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#define STH OPCD( 44)
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#define STW OPCD( 36)
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#define STD XO62( 0)
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#define STDU XO62( 1)
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#define STDX XO31(149)
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#define LD XO58( 0)
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#define LDX XO31( 21)
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#define LDU XO58( 1)
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#define LDUX XO31( 53)
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#define LWA XO58( 2)
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#define LWAX XO31(341)
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#define LQ OPCD( 56)
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#define STB OPCD( 38)
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#define STH OPCD( 44)
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#define STW OPCD( 36)
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#define STD XO62( 0)
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#define STDU XO62( 1)
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#define STDX XO31(149)
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#define STQ XO62( 2)
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#define ADDIC OPCD( 12)
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#define ADDI OPCD( 14)
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@ -2020,7 +2022,18 @@ typedef struct {
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bool tcg_target_has_memory_bswap(MemOp memop)
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{
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return true;
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TCGAtomAlign aa;
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if ((memop & MO_SIZE) <= MO_64) {
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return true;
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}
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/*
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* Reject 16-byte memop with 16-byte atomicity,
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* but do allow a pair of 64-bit operations.
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*/
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aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true);
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return aa.atom <= MO_64;
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}
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/*
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@ -2035,7 +2048,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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{
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TCGLabelQemuLdst *ldst = NULL;
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MemOp opc = get_memop(oi);
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MemOp a_bits;
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MemOp a_bits, s_bits;
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/*
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* Book II, Section 1.4, Single-Copy Atomicity, specifies:
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@ -2047,10 +2060,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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* As of 3.0, "the non-atomic access is performed as described in
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* the corresponding list", which matches MO_ATOM_SUBALIGN.
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*/
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s_bits = opc & MO_SIZE;
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h->aa = atom_and_align_for_opc(s, opc,
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have_isa_3_00 ? MO_ATOM_SUBALIGN
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: MO_ATOM_IFALIGN,
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false);
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s_bits == MO_128);
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a_bits = h->aa.align;
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#ifdef CONFIG_SOFTMMU
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@ -2060,7 +2074,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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int fast_off = TLB_MASK_TABLE_OFS(mem_index);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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unsigned s_bits = opc & MO_SIZE;
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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@ -2303,6 +2316,60 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
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}
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}
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static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg addr_reg, MemOpIdx oi, bool is_ld)
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{
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TCGLabelQemuLdst *ldst;
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HostAddress h;
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bool need_bswap;
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uint32_t insn;
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TCGReg index;
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ldst = prepare_host_addr(s, &h, addr_reg, -1, oi, is_ld);
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/* Compose the final address, as LQ/STQ have no indexing. */
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index = h.index;
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if (h.base != 0) {
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index = TCG_REG_TMP1;
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tcg_out32(s, ADD | TAB(index, h.base, h.index));
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}
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need_bswap = get_memop(oi) & MO_BSWAP;
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if (h.aa.atom == MO_128) {
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tcg_debug_assert(!need_bswap);
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tcg_debug_assert(datalo & 1);
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tcg_debug_assert(datahi == datalo - 1);
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insn = is_ld ? LQ : STQ;
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tcg_out32(s, insn | TAI(datahi, index, 0));
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} else {
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TCGReg d1, d2;
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if (HOST_BIG_ENDIAN ^ need_bswap) {
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d1 = datahi, d2 = datalo;
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} else {
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d1 = datalo, d2 = datahi;
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}
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if (need_bswap) {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 8);
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insn = is_ld ? LDBRX : STDBRX;
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tcg_out32(s, insn | TAB(d1, 0, index));
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tcg_out32(s, insn | TAB(d2, index, TCG_REG_R0));
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} else {
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insn = is_ld ? LD : STD;
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tcg_out32(s, insn | TAI(d1, index, 0));
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tcg_out32(s, insn | TAI(d2, index, 8));
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}
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}
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if (ldst) {
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ldst->type = TCG_TYPE_I128;
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ldst->datalo_reg = datalo;
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ldst->datahi_reg = datahi;
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ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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}
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static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
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{
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int i;
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@ -2860,6 +2927,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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args[4], TCG_TYPE_I64);
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}
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break;
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case INDEX_op_qemu_ld_a32_i128:
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case INDEX_op_qemu_ld_a64_i128:
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tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
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tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true);
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break;
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case INDEX_op_qemu_st_a64_i32:
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if (TCG_TARGET_REG_BITS == 32) {
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@ -2889,6 +2961,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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args[4], TCG_TYPE_I64);
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}
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break;
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case INDEX_op_qemu_st_a32_i128:
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case INDEX_op_qemu_st_a64_i128:
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tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
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tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false);
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break;
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case INDEX_op_setcond_i32:
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tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
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@ -3722,6 +3799,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_qemu_st_a64_i64:
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return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I4(r, r, r, r);
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case INDEX_op_qemu_ld_a32_i128:
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case INDEX_op_qemu_ld_a64_i128:
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return C_O2_I1(o, m, r);
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case INDEX_op_qemu_st_a32_i128:
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case INDEX_op_qemu_st_a64_i128:
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return C_O0_I3(o, m, r);
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case INDEX_op_add_vec:
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case INDEX_op_sub_vec:
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case INDEX_op_mul_vec:
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@ -149,7 +149,8 @@ extern bool have_vsx;
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#define TCG_TARGET_HAS_mulsh_i64 1
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#endif
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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#define TCG_TARGET_HAS_qemu_ldst_i128 \
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(TCG_TARGET_REG_BITS == 64 && have_isa_2_07)
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/*
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* While technically Altivec could support V64, it has no 64-bit store
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