mirror of https://github.com/proxmox/mirror_qemu
aspeed/i2c: Add support for DMA transfers
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA transfers to and from DRAM. A pair of registers defines the buffer address and the length of the DMA transfer. The address should be aligned on 4 bytes and the maximum length should not exceed 4K. The receive or transmit DMA transfer can then be initiated with specific bits in the Command/Status register of the controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Cédric Le Goater
Peter Maydell
parent
95b56e173e
commit
545d6bef70
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@ -343,6 +343,11 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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}
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/* I2C */
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object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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@ -311,6 +311,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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}
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/* I2C */
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object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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@ -23,8 +23,11 @@
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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/* I2C Global Register */
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@ -138,7 +141,8 @@
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#define I2CD_BYTE_BUF_TX_MASK 0xff
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#define I2CD_BYTE_BUF_RX_SHIFT 8
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#define I2CD_BYTE_BUF_RX_MASK 0xff
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#define I2CD_DMA_ADDR 0x24 /* DMA Buffer Address */
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#define I2CD_DMA_LEN 0x28 /* DMA Transfer Length < 4KB */
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static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
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{
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@ -165,6 +169,7 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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AspeedI2CBus *bus = opaque;
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AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
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switch (offset) {
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case I2CD_FUN_CTRL_REG:
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@ -183,6 +188,18 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
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return bus->buf;
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case I2CD_CMD_REG:
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return bus->cmd | (i2c_bus_busy(bus->bus) << 16);
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case I2CD_DMA_ADDR:
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if (!aic->has_dma) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
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return -1;
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}
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return bus->dma_addr;
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case I2CD_DMA_LEN:
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if (!aic->has_dma) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
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return -1;
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}
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return bus->dma_len;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
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@ -201,6 +218,24 @@ static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
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return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;
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}
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static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data)
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{
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MemTxResult result;
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AspeedI2CState *s = bus->controller;
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result = address_space_read(&s->dram_as, bus->dma_addr,
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MEMTXATTRS_UNSPECIFIED, data, 1);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n",
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__func__, bus->dma_addr);
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return -1;
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}
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bus->dma_addr++;
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bus->dma_len--;
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return 0;
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}
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static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start)
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{
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AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
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@ -217,6 +252,16 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start)
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}
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}
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bus->cmd &= ~I2CD_TX_BUFF_ENABLE;
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} else if (bus->cmd & I2CD_TX_DMA_ENABLE) {
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while (bus->dma_len) {
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uint8_t data;
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aspeed_i2c_dma_read(bus, &data);
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ret = i2c_send(bus->bus, data);
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if (ret) {
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break;
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}
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}
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bus->cmd &= ~I2CD_TX_DMA_ENABLE;
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} else {
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ret = i2c_send(bus->bus, bus->buf);
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}
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@ -242,6 +287,24 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)
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bus->pool_ctrl &= ~(0xff << 24);
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bus->pool_ctrl |= (i & 0xff) << 24;
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bus->cmd &= ~I2CD_RX_BUFF_ENABLE;
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} else if (bus->cmd & I2CD_RX_DMA_ENABLE) {
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uint8_t data;
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while (bus->dma_len) {
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MemTxResult result;
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data = i2c_recv(bus->bus);
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result = address_space_write(&s->dram_as, bus->dma_addr,
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MEMTXATTRS_UNSPECIFIED, &data, 1);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n",
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__func__, bus->dma_addr);
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return;
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}
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bus->dma_addr++;
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bus->dma_len--;
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}
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bus->cmd &= ~I2CD_RX_DMA_ENABLE;
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} else {
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data = i2c_recv(bus->bus);
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bus->buf = (data & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
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@ -268,6 +331,11 @@ static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus)
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uint8_t *pool_base = aic->bus_pool_base(bus);
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return pool_base[0];
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} else if (bus->cmd & I2CD_TX_DMA_ENABLE) {
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uint8_t data;
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aspeed_i2c_dma_read(bus, &data);
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return data;
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} else {
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return bus->buf;
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}
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@ -344,6 +412,10 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
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*/
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pool_start++;
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}
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} else if (bus->cmd & I2CD_TX_DMA_ENABLE) {
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if (bus->dma_len == 0) {
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bus->cmd &= ~I2CD_M_TX_CMD;
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}
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} else {
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bus->cmd &= ~I2CD_M_TX_CMD;
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}
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@ -447,9 +519,35 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
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break;
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}
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if (!aic->has_dma &&
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value & (I2CD_RX_DMA_ENABLE | I2CD_TX_DMA_ENABLE)) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
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break;
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}
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aspeed_i2c_bus_handle_cmd(bus, value);
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aspeed_i2c_bus_raise_interrupt(bus);
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break;
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case I2CD_DMA_ADDR:
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if (!aic->has_dma) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
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break;
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}
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bus->dma_addr = value & 0xfffffffc;
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break;
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case I2CD_DMA_LEN:
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if (!aic->has_dma) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
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break;
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}
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bus->dma_len = value & 0xfff;
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if (!bus->dma_len) {
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qemu_log_mask(LOG_UNIMP, "%s: invalid DMA length\n", __func__);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
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@ -542,8 +640,8 @@ static const MemoryRegionOps aspeed_i2c_pool_ops = {
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static const VMStateDescription aspeed_i2c_bus_vmstate = {
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.name = TYPE_ASPEED_I2C,
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.version_id = 2,
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.minimum_version_id = 2,
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.version_id = 3,
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.minimum_version_id = 3,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(id, AspeedI2CBus),
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VMSTATE_UINT32(ctrl, AspeedI2CBus),
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@ -553,6 +651,8 @@ static const VMStateDescription aspeed_i2c_bus_vmstate = {
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VMSTATE_UINT32(cmd, AspeedI2CBus),
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VMSTATE_UINT32(buf, AspeedI2CBus),
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VMSTATE_UINT32(pool_ctrl, AspeedI2CBus),
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VMSTATE_UINT32(dma_addr, AspeedI2CBus),
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VMSTATE_UINT32(dma_len, AspeedI2CBus),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -584,6 +684,8 @@ static void aspeed_i2c_reset(DeviceState *dev)
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s->busses[i].intr_status = 0;
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s->busses[i].cmd = 0;
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s->busses[i].buf = 0;
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s->busses[i].dma_addr = 0;
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s->busses[i].dma_len = 0;
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i2c_end_transfer(s->busses[i].bus);
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}
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}
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@ -640,14 +742,30 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
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memory_region_init_io(&s->pool_iomem, OBJECT(s), &aspeed_i2c_pool_ops, s,
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"aspeed.i2c-pool", aic->pool_size);
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memory_region_add_subregion(&s->iomem, aic->pool_base, &s->pool_iomem);
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if (aic->has_dma) {
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if (!s->dram_mr) {
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error_setg(errp, TYPE_ASPEED_I2C ": 'dram' link not set");
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return;
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}
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address_space_init(&s->dram_as, s->dram_mr, "dma-dram");
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}
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}
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static Property aspeed_i2c_properties[] = {
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DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr,
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TYPE_MEMORY_REGION, MemoryRegion *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void aspeed_i2c_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &aspeed_i2c_vmstate;
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dc->reset = aspeed_i2c_reset;
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dc->props = aspeed_i2c_properties;
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dc->realize = aspeed_i2c_realize;
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dc->desc = "Aspeed I2C Controller";
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}
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@ -721,6 +839,7 @@ static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data)
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aic->pool_base = 0x200;
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aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base;
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aic->check_sram = true;
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aic->has_dma = true;
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}
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static const TypeInfo aspeed_2500_i2c_info = {
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@ -753,6 +872,7 @@ static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data)
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aic->pool_size = 0x200;
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aic->pool_base = 0xC00;
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aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base;
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aic->has_dma = true;
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}
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static const TypeInfo aspeed_2600_i2c_info = {
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@ -52,6 +52,8 @@ typedef struct AspeedI2CBus {
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uint32_t cmd;
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uint32_t buf;
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uint32_t pool_ctrl;
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uint32_t dma_addr;
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uint32_t dma_len;
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} AspeedI2CBus;
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typedef struct AspeedI2CState {
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@ -66,6 +68,8 @@ typedef struct AspeedI2CState {
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uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];
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AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
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MemoryRegion *dram_mr;
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AddressSpace dram_as;
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} AspeedI2CState;
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#define ASPEED_I2C_CLASS(klass) \
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@ -85,6 +89,7 @@ typedef struct AspeedI2CClass {
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hwaddr pool_base;
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uint8_t *(*bus_pool_base)(AspeedI2CBus *);
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bool check_sram;
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bool has_dma;
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} AspeedI2CClass;
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