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softmmu: provide softmmu access type enum 

New MIPS features depend on the access type and enum is more convenient than
using the numbers directly.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
master
Leon Alrae 2014-07-07 11:23:56 +01:00
parent e98c0d179f
commit 55e9409366
2 changed files with 22 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/exec/cpu-common.h
View File

@ -26,6 +26,12 @@ typedef struct CPUListState {
FILE *file; FILE *file;
} CPUListState; } CPUListState;
typedef enum MMUAccessType {
MMU_DATA_LOAD = 0,
MMU_DATA_STORE = 1,
MMU_INST_FETCH = 2
} MMUAccessType;
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
enum device_endian { enum device_endian {

26
softmmu_template.h
View File

@ -67,10 +67,10 @@
#endif #endif
#ifdef SOFTMMU_CODE_ACCESS #ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2 #define READ_ACCESS_TYPE MMU_INST_FETCH
#define ADDR_READ addr_code #define ADDR_READ addr_code
#else #else
#define READ_ACCESS_TYPE 0 #define READ_ACCESS_TYPE MMU_DATA_LOAD
#define ADDR_READ addr_read #define ADDR_READ addr_read
#endif #endif
@ -396,11 +396,12 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
#ifdef ALIGNED_ONLY #ifdef ALIGNED_ONLY
if ((addr & (DATA_SIZE - 1)) != 0) { if ((addr & (DATA_SIZE - 1)) != 0) {
cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
mmu_idx, retaddr);
} }
#endif #endif
if (!VICTIM_TLB_HIT(addr_write)) { if (!VICTIM_TLB_HIT(addr_write)) {
tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
} }
tlb_addr = env->tlb_table[mmu_idx][index].addr_write; tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
} }
@ -427,7 +428,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
int i; int i;
do_unaligned_access: do_unaligned_access:
#ifdef ALIGNED_ONLY #ifdef ALIGNED_ONLY
cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
mmu_idx, retaddr);
#endif #endif
/* XXX: not efficient, but simple */ /* XXX: not efficient, but simple */
/* Note: relies on the fact that tlb_fill() does not remove the /* Note: relies on the fact that tlb_fill() does not remove the
@ -446,7 +448,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
/* Handle aligned access or unaligned access in the same page. */ /* Handle aligned access or unaligned access in the same page. */
#ifdef ALIGNED_ONLY #ifdef ALIGNED_ONLY
if ((addr & (DATA_SIZE - 1)) != 0) { if ((addr & (DATA_SIZE - 1)) != 0) {
cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
mmu_idx, retaddr);
} }
#endif #endif
@ -474,11 +477,12 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
#ifdef ALIGNED_ONLY #ifdef ALIGNED_ONLY
if ((addr & (DATA_SIZE - 1)) != 0) { if ((addr & (DATA_SIZE - 1)) != 0) {
cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
mmu_idx, retaddr);
} }
#endif #endif
if (!VICTIM_TLB_HIT(addr_write)) { if (!VICTIM_TLB_HIT(addr_write)) {
tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
} }
tlb_addr = env->tlb_table[mmu_idx][index].addr_write; tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
} }
@ -505,7 +509,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
int i; int i;
do_unaligned_access: do_unaligned_access:
#ifdef ALIGNED_ONLY #ifdef ALIGNED_ONLY
cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
mmu_idx, retaddr);
#endif #endif
/* XXX: not efficient, but simple */ /* XXX: not efficient, but simple */
/* Note: relies on the fact that tlb_fill() does not remove the /* Note: relies on the fact that tlb_fill() does not remove the
@ -524,7 +529,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
/* Handle aligned access or unaligned access in the same page. */ /* Handle aligned access or unaligned access in the same page. */
#ifdef ALIGNED_ONLY #ifdef ALIGNED_ONLY
if ((addr & (DATA_SIZE - 1)) != 0) { if ((addr & (DATA_SIZE - 1)) != 0) {
cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
mmu_idx, retaddr);
} }
#endif #endif