mirror of https://github.com/proxmox/mirror_qemu
target/ppc: Style fixes for mem_helper.c
Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>master
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6f7a69936b
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5a2c8b9ed9
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@ -27,7 +27,7 @@
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#include "internal.h"
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#include "internal.h"
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#include "qemu/atomic128.h"
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#include "qemu/atomic128.h"
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//#define DEBUG_OP
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/* #define DEBUG_OP */
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static inline bool needs_byteswap(const CPUPPCState *env)
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static inline bool needs_byteswap(const CPUPPCState *env)
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{
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{
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@ -103,10 +103,11 @@ void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
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do_lsw(env, addr, nb, reg, GETPC());
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do_lsw(env, addr, nb, reg, GETPC());
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}
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}
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/* PPC32 specification says we must generate an exception if
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/*
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* rA is in the range of registers to be loaded.
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* PPC32 specification says we must generate an exception if rA is in
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* In an other hand, IBM says this is valid, but rA won't be loaded.
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* the range of registers to be loaded. In an other hand, IBM says
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* For now, I'll follow the spec...
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* this is valid, but rA won't be loaded. For now, I'll follow the
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* spec...
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*/
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*/
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void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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uint32_t ra, uint32_t rb)
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uint32_t ra, uint32_t rb)
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@ -199,7 +200,8 @@ void helper_dcbzep(CPUPPCState *env, target_ulong addr, uint32_t opcode)
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void helper_icbi(CPUPPCState *env, target_ulong addr)
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void helper_icbi(CPUPPCState *env, target_ulong addr)
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{
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{
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addr &= ~(env->dcache_line_size - 1);
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addr &= ~(env->dcache_line_size - 1);
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/* Invalidate one cache line :
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/*
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* Invalidate one cache line :
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* PowerPC specification says this is to be treated like a load
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* PowerPC specification says this is to be treated like a load
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* (not a fetch) by the MMU. To be sure it will be so,
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* (not a fetch) by the MMU. To be sure it will be so,
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* do the load "by hand".
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* do the load "by hand".
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@ -346,17 +348,19 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
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#define LO_IDX 0
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#define LO_IDX 0
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#endif
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#endif
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/* We use msr_le to determine index ordering in a vector. However,
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/*
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byteswapping is not simply controlled by msr_le. We also need to take
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* We use msr_le to determine index ordering in a vector. However,
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into account endianness of the target. This is done for the little-endian
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* byteswapping is not simply controlled by msr_le. We also need to
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PPC64 user-mode target. */
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* take into account endianness of the target. This is done for the
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* little-endian PPC64 user-mode target.
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*/
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#define LVE(name, access, swap, element) \
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#define LVE(name, access, swap, element) \
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void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
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void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
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target_ulong addr) \
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target_ulong addr) \
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{ \
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{ \
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size_t n_elems = ARRAY_SIZE(r->element); \
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size_t n_elems = ARRAY_SIZE(r->element); \
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int adjust = HI_IDX*(n_elems - 1); \
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int adjust = HI_IDX * (n_elems - 1); \
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int sh = sizeof(r->element[0]) >> 1; \
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int sh = sizeof(r->element[0]) >> 1; \
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int index = (addr & 0xf) >> sh; \
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int index = (addr & 0xf) >> sh; \
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if (msr_le) { \
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if (msr_le) { \
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@ -476,12 +480,13 @@ VSX_STXVL(stxvll, 1)
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void helper_tbegin(CPUPPCState *env)
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void helper_tbegin(CPUPPCState *env)
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{
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{
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/* As a degenerate implementation, always fail tbegin. The reason
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/*
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* As a degenerate implementation, always fail tbegin. The reason
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* given is "Nesting overflow". The "persistent" bit is set,
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* given is "Nesting overflow". The "persistent" bit is set,
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* providing a hint to the error handler to not retry. The TFIAR
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* providing a hint to the error handler to not retry. The TFIAR
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* captures the address of the failure, which is this tbegin
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* captures the address of the failure, which is this tbegin
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* instruction. Instruction execution will continue with the
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* instruction. Instruction execution will continue with the next
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* next instruction in memory, which is precisely what we want.
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* instruction in memory, which is precisely what we want.
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*/
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*/
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env->spr[SPR_TEXASR] =
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env->spr[SPR_TEXASR] =
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