mirror of https://github.com/proxmox/mirror_qemu
hw/display/qxl: Suppress clang-7 warning about misaligned atomic operation
If QEMU is compiled with clang-7 it results in the warning: hw/display/qxl.c:1884:19: error: misaligned or large atomic operation may incur significant performance penalty [-Werror,-Watomic-alignment] old_pending = atomic_fetch_or(&d->ram->int_pending, le_events); ^ This is because the Spice headers forgot to define the QXLRam struct with the '__aligned__(4)' attribute. clang 7 and newer will thus warn that the access here to int_pending might not be 4-aligned (because the QXLRam object d->ram points at might start at a misaligned address). In fact we set up d->ram in init_qxl_ram() so it always starts at a 4K boundary, so we know the atomic access here is OK. Newer Spice versions (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1) will fix the bug; for older Spice versions, work around it by telling the compiler explicitly that the alignment is OK using __builtin_assume_aligned(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180927155538.699-1-peter.maydell@linaro.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>master
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1242429b20
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5a358b39f5
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@ -1893,7 +1893,31 @@ static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
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trace_qxl_send_events_vm_stopped(d->id, events);
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trace_qxl_send_events_vm_stopped(d->id, events);
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return;
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return;
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}
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}
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old_pending = atomic_fetch_or(&d->ram->int_pending, le_events);
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/*
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* Older versions of Spice forgot to define the QXLRam struct
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* with the '__aligned__(4)' attribute. clang 7 and newer will
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* thus warn that atomic_fetch_or(&d->ram->int_pending, ...)
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* might be a misaligned atomic access, and will generate an
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* out-of-line call for it, which results in a link error since
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* we don't currently link against libatomic.
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*
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* In fact we set up d->ram in init_qxl_ram() so it always starts
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* at a 4K boundary, so we know that &d->ram->int_pending is
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* naturally aligned for a uint32_t. Newer Spice versions
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* (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1)
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* will fix the bug directly. To deal with older versions,
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* we tell the compiler to assume the address really is aligned.
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* Any compiler which cares about the misalignment will have
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* __builtin_assume_aligned.
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*/
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#ifdef HAS_ASSUME_ALIGNED
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#define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
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#else
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#define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
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#endif
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old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
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le_events);
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if ((old_pending & le_events) == le_events) {
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if ((old_pending & le_events) == le_events) {
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return;
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return;
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}
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}
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@ -122,6 +122,15 @@
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#ifndef __has_feature
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#ifndef __has_feature
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#define __has_feature(x) 0 /* compatibility with non-clang compilers */
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#define __has_feature(x) 0 /* compatibility with non-clang compilers */
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#endif
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#endif
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#ifndef __has_builtin
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#define __has_builtin(x) 0 /* compatibility with non-clang compilers */
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#endif
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#if __has_builtin(__builtin_assume_aligned) || QEMU_GNUC_PREREQ(4, 7)
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#define HAS_ASSUME_ALIGNED
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#endif
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/* Implement C11 _Generic via GCC builtins. Example:
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/* Implement C11 _Generic via GCC builtins. Example:
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*
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*
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* QEMU_GENERIC(x, (float, sinf), (long double, sinl), sin) (x)
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* QEMU_GENERIC(x, (float, sinf), (long double, sinl), sin) (x)
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