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target/mips/tx79: Move PCPYH opcode to decodetree 

Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree.
Remove unnecessary code / comments.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-12-f4bug@amsat.org>
master
Philippe Mathieu-Daudé 2021-02-13 11:57:56 +01:00
parent ca8def9bdb
commit 5a976c0025
3 changed files with 27 additions and 39 deletions
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39
target/mips/translate.c
View File

@ -24062,42 +24062,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
* PEXTUW
*/
/*
* PCPYH rd, rt
*
* Parallel Copy Halfword
*
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-----------+---------+---------+---------+---------+-----------+
* | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 |
* +-----------+---------+---------+---------+---------+-----------+
*/
static void gen_mmi_pcpyh(DisasContext *ctx)
{
uint32_t pd, rt, rd;
uint32_t opcode;
opcode = ctx->opcode;
pd = extract32(opcode, 21, 5);
rt = extract32(opcode, 16, 5);
rd = extract32(opcode, 11, 5);
if (unlikely(pd != 0)) {
gen_reserved_instruction(ctx);
} else if (rd == 0) {
/* nop */
} else if (rt == 0) {
tcg_gen_movi_i64(cpu_gpr[rd], 0);
tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
} else {
tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_gpr[rt], 16, 16);
tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rd], cpu_gpr[rd], 32, 32);
tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt], cpu_gpr_hi[rt], 16, 16);
tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rd], cpu_gpr_hi[rd], 32, 32);
}
}
/*
* PCPYLD rd, rs, rt
*
@ -25016,9 +24980,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
case MMI_OPC_3_PCPYH:
gen_mmi_pcpyh(ctx);
break;
case MMI_OPC_3_PCPYUD:
gen_mmi_pcpyud(ctx);
break;

5
target/mips/tx79.decode
View File

@ -17,6 +17,7 @@
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=0 sa=0
@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
@ -26,3 +27,7 @@ MFHI1 011100 0000000000 ..... 00000 010000 @rd
MTHI1 011100 ..... 0000000000 00000 010001 @rs
MFLO1 011100 0000000000 ..... 00000 010010 @rd
MTLO1 011100 ..... 0000000000 00000 010011 @rs
# MMI3
PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd

22
target/mips/tx79_translate.c
View File

@ -49,3 +49,25 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
return true;
}
/* Parallel Copy Halfword */
static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
{
if (a->rd == 0) {
/* nop */
return true;
}
if (a->rt == 0) {
tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
return true;
}
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16);
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32);
return true;
}