From 5b1e098128367d6ef7cb2d1e99a55fcf4fa9cdde Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Thu, 3 Jan 2019 19:22:19 +0100 Subject: [PATCH] target/mips: Correct the second argument type of cpu_supports_isa() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "insn_flags" bitfield was expanded from 32-bit to 64-bit in commit f9c9cd63e3. However, this was not reflected on the second argument of the function cpu_supports_isa(). By chance, this did not create some wrong behavior, since the left-most halves of all instances of the second argument are currently all zeros. However, this is still a bug waiting to happen. Correct this by changing the type of the second argument to be always 64-bit. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 2 +- target/mips/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c4da7dfbfd..473d26d6ff 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1173,7 +1173,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU bool cpu_supports_cps_smp(const char *cpu_type); -bool cpu_supports_isa(const char *cpu_type, unsigned int isa); +bool cpu_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); /* mips_int.c */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 2140ecda97..b362b03d74 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29883,7 +29883,7 @@ bool cpu_supports_cps_smp(const char *cpu_type) return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } -bool cpu_supports_isa(const char *cpu_type, unsigned int isa) +bool cpu_supports_isa(const char *cpu_type, uint64_t isa) { const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); return (mcc->cpu_def->insn_flags & isa) != 0;