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target/mips: Convert Vr54xx MACC* opcodes to decodetree 

Convert the following Integer Multiply-Accumulate opcodes:

 * MACC         Multiply, accumulate, and move LO
 * MACCHI       Multiply, accumulate, and move HI
 * MACCHIU      Unsigned multiply, accumulate, and move HI
 * MACCU        Unsigned multiply, accumulate, and move LO

Since all opcodes are generated using the same pattern, we
add the gen_helper_mult_acc_t typedef and MULT_ACC() macro
to remove boilerplate code.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-6-f4bug@amsat.org>
master
Philippe Mathieu-Daudé 2021-07-28 13:20:42 +02:00
parent 9d00539239
commit 5fa38eedbd
3 changed files with 42 additions and 16 deletions
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16
target/mips/tcg/translate.c
View File

@ -300,16 +300,12 @@ enum {
enum {
OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
};
@ -3780,12 +3776,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
case OPC_VR54XX_MULSU:
gen_helper_mulsu(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MACC:
gen_helper_macc(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MACCU:
gen_helper_maccu(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MSAC:
gen_helper_msac(t0, cpu_env, t0, t1);
break;
@ -3804,12 +3794,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
case OPC_VR54XX_MULSHIU:
gen_helper_mulshiu(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MACCHI:
gen_helper_macchi(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MACCHIU:
gen_helper_macchiu(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MSACHI:
gen_helper_msachi(t0, cpu_env, t0, t1);
break;

9
target/mips/tcg/vr54xx.decode
View File

@ -6,3 +6,12 @@
#
# Reference: VR5432 Microprocessor User’s Manual
# (Document Number U13751EU5V0UM00)
&r rs rt rd
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r
MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd
MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd
MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd
MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd

33
target/mips/tcg/vr54xx_translate.c
View File

@ -17,3 +17,36 @@
/* Include the auto-generated decoder. */
#include "decode-vr54xx.c.inc"
/*
* Integer Multiply-Accumulate Instructions
*
* MACC Multiply, accumulate, and move LO
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCU Unsigned multiply, accumulate, and move LO
*/
static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
void (*gen_helper_mult_acc)(TCGv, TCGv_ptr, TCGv, TCGv))
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
gen_load_gpr(t0, a->rs);
gen_load_gpr(t1, a->rt);
gen_helper_mult_acc(t0, cpu_env, t0, t1);
gen_store_gpr(t0, a->rd);
tcg_temp_free(t0);
tcg_temp_free(t1);
return false;
}
TRANS(MACC, trans_mult_acc, gen_helper_macc);
TRANS(MACCHI, trans_mult_acc, gen_helper_macchi);
TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu);
TRANS(MACCU, trans_mult_acc, gen_helper_maccu);