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target/arm: Convert unconditional branch immediate to decodetree 

Convert the unconditional branch immediate insns B and BL to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-14-peter.maydell@linaro.org
master
Peter Maydell 2023-05-12 15:40:59 +01:00
parent 4240fb6175
commit 6201b2a4d0
2 changed files with 20 additions and 20 deletions
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9
target/arm/tcg/a64.decode
View File

@ -21,6 +21,7 @@
&ri rd imm
&rri_sf rd rn imm sf
&i imm
### Data Processing - Immediate
@ -104,3 +105,11 @@ UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32
EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1
EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0
# Branches
%imm26 0:s26 !function=times_4
@branch . ..... .......................... &i imm=%imm26
B 0 00101 .......................... @branch
BL 1 00101 .......................... @branch

31
target/arm/tcg/translate-a64.c
View File

@ -1319,24 +1319,19 @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
* match up with those in the manual.
*/
/* Unconditional branch (immediate)
* 31 30 26 25 0
* +----+-----------+-------------------------------------+
* | op | 0 0 1 0 1 | imm26 |
* +----+-----------+-------------------------------------+
*/
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
static bool trans_B(DisasContext *s, arg_i *a)
{
int64_t diff = sextract32(insn, 0, 26) * 4;
if (insn & (1U << 31)) {
/* BL Branch with link */
gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s));
}
/* B Branch / BL Branch with link */
reset_btype(s);
gen_goto_tb(s, 0, diff);
gen_goto_tb(s, 0, a->imm);
return true;
}
static bool trans_BL(DisasContext *s, arg_i *a)
{
gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s));
reset_btype(s);
gen_goto_tb(s, 0, a->imm);
return true;
}
/* Compare and branch (immediate)
@ -2413,10 +2408,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 25, 7)) {
case 0x0a: case 0x0b:
case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
disas_uncond_b_imm(s, insn);
break;
case 0x1a: case 0x5a: /* Compare & branch (immediate) */
disas_comp_b_imm(s, insn);
break;