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target/i386: provide 3-operand versions of unary scalar helpers 

Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations.  Adjust the
old SSE decoder to be compatible with new-style helpers.

The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
master
Paolo Bonzini 2022-09-09 11:08:18 +02:00
parent 1de9e7e612
commit 620f75566a
3 changed files with 61 additions and 25 deletions
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48
target/i386/ops_sse.h
View File

@ -617,14 +617,22 @@ void glue(helper_sqrtpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
}
#if SHIFT == 1
void helper_sqrtss(CPUX86State *env, Reg *d, Reg *s)
void helper_sqrtss(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
int i;
d->ZMM_S(0) = float32_sqrt(s->ZMM_S(0), &env->sse_status);
for (i = 1; i < 2 << SHIFT; i++) {
d->ZMM_L(i) = v->ZMM_L(i);
}
}
void helper_sqrtsd(CPUX86State *env, Reg *d, Reg *s)
void helper_sqrtsd(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
int i;
d->ZMM_D(0) = float64_sqrt(s->ZMM_D(0), &env->sse_status);
for (i = 1; i < 1 << SHIFT; i++) {
d->ZMM_Q(i) = v->ZMM_Q(i);
}
}
#endif
@ -649,14 +657,22 @@ void glue(helper_cvtpd2ps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
}
#if SHIFT == 1
void helper_cvtss2sd(CPUX86State *env, Reg *d, Reg *s)
void helper_cvtss2sd(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
int i;
d->ZMM_D(0) = float32_to_float64(s->ZMM_S(0), &env->sse_status);
for (i = 1; i < 1 << SHIFT; i++) {
d->ZMM_Q(i) = v->ZMM_Q(i);
}
}
void helper_cvtsd2ss(CPUX86State *env, Reg *d, Reg *s)
void helper_cvtsd2ss(CPUX86State *env, Reg *d, Reg *v, Reg *s)
{
int i;
d->ZMM_S(0) = float64_to_float32(s->ZMM_D(0), &env->sse_status);
for (i = 1; i < 2 << SHIFT; i++) {
d->ZMM_L(i) = v->ZMM_L(i);
}
}
#endif
@ -876,13 +892,17 @@ void glue(helper_rsqrtps, SUFFIX)(CPUX86State *env, ZMMReg *d, ZMMReg *s)
}
#if SHIFT == 1
void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *s)
void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *v, ZMMReg *s)
{
uint8_t old_flags = get_float_exception_flags(&env->sse_status);
int i;
d->ZMM_S(0) = float32_div(float32_one,
float32_sqrt(s->ZMM_S(0), &env->sse_status),
&env->sse_status);
set_float_exception_flags(old_flags, &env->sse_status);
for (i = 1; i < 2 << SHIFT; i++) {
d->ZMM_L(i) = v->ZMM_L(i);
}
}
#endif
@ -897,10 +917,14 @@ void glue(helper_rcpps, SUFFIX)(CPUX86State *env, ZMMReg *d, ZMMReg *s)
}
#if SHIFT == 1
void helper_rcpss(CPUX86State *env, ZMMReg *d, ZMMReg *s)
void helper_rcpss(CPUX86State *env, ZMMReg *d, ZMMReg *v, ZMMReg *s)
{
uint8_t old_flags = get_float_exception_flags(&env->sse_status);
int i;
d->ZMM_S(0) = float32_div(float32_one, s->ZMM_S(0), &env->sse_status);
for (i = 1; i < 2 << SHIFT; i++) {
d->ZMM_L(i) = v->ZMM_L(i);
}
set_float_exception_flags(old_flags, &env->sse_status);
}
#endif
@ -1798,11 +1822,12 @@ void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
}
#if SHIFT == 1
void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s,
uint32_t mode)
{
uint8_t old_flags = get_float_exception_flags(&env->sse_status);
signed char prev_rounding_mode;
int i;
prev_rounding_mode = env->sse_status.float_rounding_mode;
if (!(mode & (1 << 2))) {
@ -1823,6 +1848,9 @@ void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
}
d->ZMM_S(0) = float32_round_to_int(s->ZMM_S(0), &env->sse_status);
for (i = 1; i < 2 << SHIFT; i++) {
d->ZMM_L(i) = v->ZMM_L(i);
}
if (mode & (1 << 3) && !(old_flags & float_flag_inexact)) {
set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
@ -1832,11 +1860,12 @@ void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
env->sse_status.float_rounding_mode = prev_rounding_mode;
}
void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s,
uint32_t mode)
{
uint8_t old_flags = get_float_exception_flags(&env->sse_status);
signed char prev_rounding_mode;
int i;
prev_rounding_mode = env->sse_status.float_rounding_mode;
if (!(mode & (1 << 2))) {
@ -1857,6 +1886,9 @@ void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
}
d->ZMM_D(0) = float64_round_to_int(s->ZMM_D(0), &env->sse_status);
for (i = 1; i < 1 << SHIFT; i++) {
d->ZMM_Q(i) = v->ZMM_Q(i);
}
if (mode & (1 << 3) && !(old_flags & float_flag_inexact)) {
set_float_exception_flags(get_float_exception_flags(&env->sse_status) &

16
target/i386/ops_sse_header.h
View File

@ -148,8 +148,8 @@ DEF_HELPER_3(glue(pshufhw, SUFFIX), void, Reg, Reg, int)
DEF_HELPER_4(name ## sd, void, env, Reg, Reg, Reg)
#define SSE_HELPER_S3(name) \
SSE_HELPER_P3(name) \
DEF_HELPER_3(name ## ss, void, env, Reg, Reg) \
DEF_HELPER_3(name ## sd, void, env, Reg, Reg)
DEF_HELPER_4(name ## ss, void, env, Reg, Reg, Reg) \
DEF_HELPER_4(name ## sd, void, env, Reg, Reg, Reg)
#else
#define SSE_HELPER_S4(name, ...) SSE_HELPER_P4(name)
#define SSE_HELPER_S3(name, ...) SSE_HELPER_P3(name)
@ -179,8 +179,8 @@ DEF_HELPER_3(glue(cvttps2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(glue(cvttpd2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
#if SHIFT == 1
DEF_HELPER_3(cvtss2sd, void, env, Reg, Reg)
DEF_HELPER_3(cvtsd2ss, void, env, Reg, Reg)
DEF_HELPER_4(cvtss2sd, void, env, Reg, Reg, Reg)
DEF_HELPER_4(cvtsd2ss, void, env, Reg, Reg, Reg)
DEF_HELPER_3(cvtpi2ps, void, env, ZMMReg, MMXReg)
DEF_HELPER_3(cvtpi2pd, void, env, ZMMReg, MMXReg)
DEF_HELPER_3(cvtsi2ss, void, env, ZMMReg, i32)
@ -214,8 +214,8 @@ DEF_HELPER_3(glue(rsqrtps, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(glue(rcpps, SUFFIX), void, env, ZMMReg, ZMMReg)
#if SHIFT == 1
DEF_HELPER_3(rsqrtss, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(rcpss, void, env, ZMMReg, ZMMReg)
DEF_HELPER_4(rsqrtss, void, env, ZMMReg, ZMMReg, ZMMReg)
DEF_HELPER_4(rcpss, void, env, ZMMReg, ZMMReg, ZMMReg)
DEF_HELPER_3(extrq_r, void, env, ZMMReg, ZMMReg)
DEF_HELPER_4(extrq_i, void, env, ZMMReg, int, int)
DEF_HELPER_3(insertq_r, void, env, ZMMReg, ZMMReg)
@ -342,8 +342,8 @@ DEF_HELPER_3(glue(phminposuw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_4(glue(roundps, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(roundpd, SUFFIX), void, env, Reg, Reg, i32)
#if SHIFT == 1
DEF_HELPER_4(roundss_xmm, void, env, Reg, Reg, i32)
DEF_HELPER_4(roundsd_xmm, void, env, Reg, Reg, i32)
DEF_HELPER_5(roundss_xmm, void, env, Reg, Reg, Reg, i32)
DEF_HELPER_5(roundsd_xmm, void, env, Reg, Reg, Reg, i32)
#endif
DEF_HELPER_5(glue(blendps, SUFFIX), void, env, Reg, Reg, Reg, i32)
DEF_HELPER_5(glue(blendpd, SUFFIX), void, env, Reg, Reg, Reg, i32)

22
target/i386/tcg/translate.c
View File

@ -3011,6 +3011,9 @@ static bool first = true; static unsigned long limit;
#define SSE_OP(sname, dname, op, flags) OP(op, flags, \
gen_helper_##sname##_xmm, gen_helper_##dname##_xmm, NULL, NULL)
#define SSE_OP_UNARY(a, b, c, d) \
{SSE_OPF_SCALAR | SSE_OPF_V0, {{.op1 = a}, {.op1 = b}, {.op2 = c}, {.op2 = d} } }
typedef union SSEFuncs {
SSEFunc_0_epp op1;
SSEFunc_0_ppi op1i;
@ -3053,12 +3056,12 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0x2f] = OP(op1, SSE_OPF_CMP | SSE_OPF_SCALAR | SSE_OPF_V0,
gen_helper_comiss, gen_helper_comisd, NULL, NULL),
[0x50] = SSE_SPECIAL, /* movmskps, movmskpd */
[0x51] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
[0x51] = SSE_OP_UNARY(
gen_helper_sqrtps_xmm, gen_helper_sqrtpd_xmm,
gen_helper_sqrtss, gen_helper_sqrtsd),
[0x52] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
[0x52] = SSE_OP_UNARY(
gen_helper_rsqrtps_xmm, NULL, gen_helper_rsqrtss, NULL),
[0x53] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
[0x53] = SSE_OP_UNARY(
gen_helper_rcpps_xmm, NULL, gen_helper_rcpss, NULL),
[0x54] = SSE_OP(pand, pand, op2, 0), /* andps, andpd */
[0x55] = SSE_OP(pandn, pandn, op2, 0), /* andnps, andnpd */
@ -3066,9 +3069,9 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
[0x57] = SSE_OP(pxor, pxor, op2, 0), /* xorps, xorpd */
[0x58] = SSE_FOP(add),
[0x59] = SSE_FOP(mul),
[0x5a] = OP(op1, SSE_OPF_SCALAR | SSE_OPF_V0,
gen_helper_cvtps2pd_xmm, gen_helper_cvtpd2ps_xmm,
gen_helper_cvtss2sd, gen_helper_cvtsd2ss),
[0x5a] = SSE_OP_UNARY(
gen_helper_cvtps2pd_xmm, gen_helper_cvtpd2ps_xmm,
gen_helper_cvtss2sd, gen_helper_cvtsd2ss),
[0x5b] = OP(op1, SSE_OPF_V0,
gen_helper_cvtdq2ps_xmm, gen_helper_cvtps2dq_xmm,
gen_helper_cvttps2dq_xmm, NULL),
@ -3364,8 +3367,8 @@ static const struct SSEOpHelper_table6 sse_op_table6[256] = {
static const struct SSEOpHelper_table7 sse_op_table7[256] = {
[0x08] = UNARY_OP(roundps, SSE41, 0),
[0x09] = UNARY_OP(roundpd, SSE41, 0),
[0x0a] = UNARY_OP(roundss, SSE41, SSE_OPF_SCALAR),
[0x0b] = UNARY_OP(roundsd, SSE41, SSE_OPF_SCALAR),
[0x0a] = BINARY_OP(roundss, SSE41, SSE_OPF_SCALAR),
[0x0b] = BINARY_OP(roundsd, SSE41, SSE_OPF_SCALAR),
[0x0c] = BINARY_OP(blendps, SSE41, 0),
[0x0d] = BINARY_OP(blendpd, SSE41, 0),
[0x0e] = BINARY_OP(pblendw, SSE41, SSE_OPF_MMX),
@ -4640,7 +4643,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b)
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
if (sse_op_flags & SSE_OPF_V0) {
if ((sse_op_flags & SSE_OPF_V0) &&
!((sse_op_flags & SSE_OPF_SCALAR) && b1 >= 2)) {
if (sse_op_flags & SSE_OPF_SHUF) {
val = x86_ldub_code(env, s);
sse_op_fn.op1i(s->ptr0, s->ptr1, tcg_const_i32(val));