mirror of https://github.com/proxmox/mirror_qemu
microblaze: Update disasm to latest GPLv2 version.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>master
Edgar E. Iglesias
parent
7dbbbb0c9e
commit
6287462ef5
452
microblaze-dis.c
452
microblaze-dis.c
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@ -12,7 +12,8 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/*
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* Copyright (c) 2001 Xilinx, Inc. All rights reserved.
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@ -37,6 +38,9 @@ along with this program; if not, see <http://www.gnu.org/licenses/>. */
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#define STATIC_TABLE
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#define DEFINE_TABLE
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#define TRUE 1
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#define FALSE 0
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#ifndef MICROBLAZE_OPC
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#define MICROBLAZE_OPC
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/* Assembler instructions for Xilinx's microblaze processor
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@ -54,7 +58,8 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/*
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* Copyright (c) 2001 Xilinx, Inc. All rights reserved.
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@ -99,17 +104,33 @@ along with this program; if not, see <http://www.gnu.org/licenses/>. */
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enum microblaze_instr {
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add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu,
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addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
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addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, mulh, mulhu, mulhsu,
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idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
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ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
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andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, wic, wdc, mts, mfs, br, brd,
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andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd,
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brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
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bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
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imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
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brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
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bgtid, bgei, bgeid, lbu, lhu, lw, sb, sh, sw, lbui, lhui, lwi,
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bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
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sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
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fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, invalid_inst } ;
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fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, fint, fsqrt,
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tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
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eget, ecget, neget, necget, eput, ecput, neput, necput,
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teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
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aget, caget, naget, ncaget, aput, caput, naput, ncaput,
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taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput,
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eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput,
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teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput,
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getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd,
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putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd,
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egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd,
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eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd,
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agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd,
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aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
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eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
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eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
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invalid_inst } ;
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enum microblaze_instr_type {
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arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst,
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@ -126,15 +147,38 @@ enum microblaze_instr_type {
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#define REG_EAR_MASK 0x8003
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#define REG_ESR_MASK 0x8005
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#define REG_FSR_MASK 0x8007
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#define REG_BTR_MASK 0x800b
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#define REG_EDR_MASK 0x800d
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#define REG_PVR_MASK 0xa000
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#define REG_PID_MASK 0x9000
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#define REG_ZPR_MASK 0x9001
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#define REG_TLBX_MASK 0x9002
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#define REG_TLBLO_MASK 0x9003
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#define REG_TLBHI_MASK 0x9004
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#define REG_TLBSX_MASK 0x9005
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#define MIN_REGNUM 0
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#define MAX_REGNUM 31
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#define MIN_PVR_REGNUM 0
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#define MAX_PVR_REGNUM 15
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#define REG_PC 32 /* PC */
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#define REG_MSR 33 /* machine status reg */
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#define REG_EAR 35 /* Exception reg */
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#define REG_ESR 37 /* Exception reg */
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#define REG_FSR 39 /* FPU Status reg */
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#define REG_BTR 43 /* Branch Target reg */
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#define REG_EDR 45 /* Exception reg */
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#define REG_PVR 40960 /* Program Verification reg */
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#define REG_PID 36864 /* MMU: Process ID reg */
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#define REG_ZPR 36865 /* MMU: Zone Protect reg */
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#define REG_TLBX 36866 /* MMU: TLB Index reg */
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#define REG_TLBLO 36867 /* MMU: TLB Low reg */
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#define REG_TLBHI 36868 /* MMU: TLB High reg */
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#define REG_TLBSX 36869 /* MMU: TLB Search Index reg */
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/* alternate names for gen purpose regs */
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#define REG_SP 1 /* stack pointer */
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@ -159,11 +203,11 @@ enum microblaze_instr_type {
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#define IMM5_MASK 0x0000001F
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// imm mask for get, put instructions
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#define IMM12_MASK 0x00000FFF
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// FSL imm mask for get, put instructions
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#define RFSL_MASK 0x000000F
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// imm mask for msrset, msrclr instructions
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#define IMM14_MASK 0x00003FFF
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#define IMM15_MASK 0x00007FFF
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#endif /* MICROBLAZE-OPCM */
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@ -182,18 +226,21 @@ enum microblaze_instr_type {
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#define INST_TYPE_R1 12
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// new instn type for barrel shift imms
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#define INST_TYPE_RD_R1_IMM5 13
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#define INST_TYPE_RD_IMM12 14
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#define INST_TYPE_R1_IMM12 15
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#define INST_TYPE_RD_RFSL 14
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#define INST_TYPE_R1_RFSL 15
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// new insn type for insn cache
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#define INST_TYPE_RD_R1_SPECIAL 16
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// new insn type for msrclr, msrset insns.
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#define INST_TYPE_RD_IMM14 17
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#define INST_TYPE_RD_IMM15 17
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// new insn type for tuqula rd - addik rd, r0, 42
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#define INST_TYPE_RD 18
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// new insn type for t*put
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#define INST_TYPE_RFSL 19
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#define INST_TYPE_NONE 25
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@ -210,24 +257,25 @@ enum microblaze_instr_type {
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#define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16 */
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#define OPCODE_MASK_H12 0xFFFF0000 /* High 16 */
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#define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits */
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#define OPCODE_MASK_H13S 0xFFE0FFF0 /* High 11 and 15:1 bits and last nibble of last byte for spr */
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#define OPCODE_MASK_H23S 0xFC1FFFF0 /* High 6, 20-16 and 15:1 bits and last nibble of last byte for spr */
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#define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last nibble of last byte for spr */
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#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last nibble of last byte for spr */
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#define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits */
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#define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits */
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#define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits */
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#define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits */
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#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits */
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#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22 */
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#define OPCODE_MASK_H32 0xFC00F000 /* High 6 bits and bit 16, 17, 18 and 19*/
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#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21 */
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#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits */
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#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26 */
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// New Mask for msrset, msrclr insns.
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#define OPCODE_MASK_H23N 0xFC1FC000 /* High 6 and bits 12 - 18 */
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#define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16 */
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#define DELAY_SLOT 1
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#define NO_DELAY_SLOT 0
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#define MAX_OPCODES 149
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#define MAX_OPCODES 280
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struct op_code_struct {
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const char *name;
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@ -262,19 +310,22 @@ struct op_code_struct {
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{"addikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst },
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{"rsubikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst },
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{"mul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst },
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{"mulh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst },
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{"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
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{"mulhsu",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst },
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{"idiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst },
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{"idivu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst },
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{"bsll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst },
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{"bsra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst },
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{"bsrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst },
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{"get", INST_TYPE_RD_IMM12, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst },
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{"put", INST_TYPE_R1_IMM12, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst },
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{"nget", INST_TYPE_RD_IMM12, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst },
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{"nput", INST_TYPE_R1_IMM12, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst },
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{"cget", INST_TYPE_RD_IMM12, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst },
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{"cput", INST_TYPE_R1_IMM12, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst },
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{"ncget", INST_TYPE_RD_IMM12, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
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{"ncput", INST_TYPE_R1_IMM12, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
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{"get", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst },
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{"put", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst },
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{"nget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst },
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{"nput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst },
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{"cget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst },
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{"cput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst },
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{"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
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{"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
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{"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
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{"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
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{"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
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@ -294,6 +345,8 @@ struct op_code_struct {
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{"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
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{"wic", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
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{"wdc", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
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{"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
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{"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
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{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
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{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
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{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
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@ -346,9 +399,11 @@ struct op_code_struct {
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{"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
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{"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
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{"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
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{"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
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{"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
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{"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
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{"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
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{"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
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{"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
|
||||
{"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
|
||||
{"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
|
||||
|
|
@ -364,8 +419,8 @@ struct op_code_struct {
|
|||
{"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra */
|
||||
{"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
|
||||
{"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
|
||||
{"msrset",INST_TYPE_RD_IMM14, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
|
||||
{"msrclr",INST_TYPE_RD_IMM14, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
|
||||
{"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
|
||||
{"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
|
||||
{"fadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
|
||||
{"frsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
|
||||
{"fmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
|
||||
|
|
@ -377,24 +432,155 @@ struct op_code_struct {
|
|||
{"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst },
|
||||
{"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst },
|
||||
{"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst },
|
||||
{""}
|
||||
{"flt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst },
|
||||
{"fint", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst },
|
||||
{"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst },
|
||||
{"tget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst },
|
||||
{"tcget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget, anyware_inst },
|
||||
{"tnget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget, anyware_inst },
|
||||
{"tncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst },
|
||||
{"tput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput, anyware_inst },
|
||||
{"tcput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst },
|
||||
{"tnput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst },
|
||||
{"tncput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst },
|
||||
|
||||
{"eget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst },
|
||||
{"ecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst },
|
||||
{"neget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst },
|
||||
{"necget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst },
|
||||
{"eput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput, anyware_inst },
|
||||
{"ecput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst },
|
||||
{"neput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst },
|
||||
{"necput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst },
|
||||
|
||||
{"teget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst },
|
||||
{"tecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst },
|
||||
{"tneget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst },
|
||||
{"tnecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst },
|
||||
{"teput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput, anyware_inst },
|
||||
{"tecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst },
|
||||
{"tneput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst },
|
||||
{"tnecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst },
|
||||
|
||||
{"aget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst },
|
||||
{"caget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst },
|
||||
{"naget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst },
|
||||
{"ncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst },
|
||||
{"aput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput, anyware_inst },
|
||||
{"caput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst },
|
||||
{"naput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst },
|
||||
{"ncaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst },
|
||||
|
||||
{"taget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst },
|
||||
{"tcaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst },
|
||||
{"tnaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst },
|
||||
{"tncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst },
|
||||
{"taput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput, anyware_inst },
|
||||
{"tcaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst },
|
||||
{"tnaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst },
|
||||
{"tncaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst },
|
||||
|
||||
{"eaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst },
|
||||
{"ecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst },
|
||||
{"neaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst },
|
||||
{"necaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst },
|
||||
{"eaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput, anyware_inst },
|
||||
{"ecaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst },
|
||||
{"neaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst },
|
||||
{"necaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst },
|
||||
|
||||
{"teaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst },
|
||||
{"tecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst },
|
||||
{"tneaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst },
|
||||
{"tnecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst },
|
||||
{"teaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput, anyware_inst },
|
||||
{"tecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst },
|
||||
{"tneaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst },
|
||||
{"tnecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst },
|
||||
|
||||
{"getd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst },
|
||||
{"tgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst },
|
||||
{"cgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst },
|
||||
{"tcgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd, anyware_inst },
|
||||
{"ngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd, anyware_inst },
|
||||
{"tngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd, anyware_inst },
|
||||
{"ncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd, anyware_inst },
|
||||
{"tncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst },
|
||||
{"putd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd, anyware_inst },
|
||||
{"tputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd, anyware_inst },
|
||||
{"cputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd, anyware_inst },
|
||||
{"tcputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd, anyware_inst },
|
||||
{"nputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd, anyware_inst },
|
||||
{"tnputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst },
|
||||
{"ncputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst },
|
||||
{"tncputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst },
|
||||
|
||||
{"egetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst },
|
||||
{"tegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst },
|
||||
{"ecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst },
|
||||
{"tecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd, anyware_inst },
|
||||
{"negetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd, anyware_inst },
|
||||
{"tnegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd, anyware_inst },
|
||||
{"necgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd, anyware_inst },
|
||||
{"tnecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst },
|
||||
{"eputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd, anyware_inst },
|
||||
{"teputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd, anyware_inst },
|
||||
{"ecputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd, anyware_inst },
|
||||
{"tecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd, anyware_inst },
|
||||
{"neputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd, anyware_inst },
|
||||
{"tneputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst },
|
||||
{"necputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst },
|
||||
{"tnecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst },
|
||||
|
||||
{"agetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst },
|
||||
{"tagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst },
|
||||
{"cagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst },
|
||||
{"tcagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd, anyware_inst },
|
||||
{"nagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd, anyware_inst },
|
||||
{"tnagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd, anyware_inst },
|
||||
{"ncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd, anyware_inst },
|
||||
{"tncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst },
|
||||
{"aputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd, anyware_inst },
|
||||
{"taputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd, anyware_inst },
|
||||
{"caputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd, anyware_inst },
|
||||
{"tcaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd, anyware_inst },
|
||||
{"naputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd, anyware_inst },
|
||||
{"tnaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst },
|
||||
{"ncaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst },
|
||||
{"tncaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst },
|
||||
|
||||
{"eagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst },
|
||||
{"teagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst },
|
||||
{"ecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst },
|
||||
{"tecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd, anyware_inst },
|
||||
{"neagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd, anyware_inst },
|
||||
{"tneagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd, anyware_inst },
|
||||
{"necagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd, anyware_inst },
|
||||
{"tnecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst },
|
||||
{"eaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd, anyware_inst },
|
||||
{"teaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd, anyware_inst },
|
||||
{"ecaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd, anyware_inst },
|
||||
{"tecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd, anyware_inst },
|
||||
{"neaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd, anyware_inst },
|
||||
{"tneaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd, anyware_inst },
|
||||
{"necaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst },
|
||||
{"tnecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
|
||||
{"", 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
/* prefix for register names */
|
||||
char register_prefix[] = "r";
|
||||
char special_register_prefix[] = "spr";
|
||||
char fsl_register_prefix[] = "rfsl";
|
||||
char pvr_register_prefix[] = "rpvr";
|
||||
|
||||
|
||||
/* #defines for valid immediate range */
|
||||
#define MIN_IMM 0x80000000
|
||||
#define MAX_IMM 0x7fffffff
|
||||
#define MIN_IMM ((int) 0x80000000)
|
||||
#define MAX_IMM ((int) 0x7fffffff)
|
||||
|
||||
#define MIN_IMM12 0x000
|
||||
#define MAX_IMM12 0x7ff
|
||||
|
||||
#define MIN_IMM14 0x0000
|
||||
#define MAX_IMM14 0x1fff
|
||||
#define MIN_IMM15 ((int) 0x0000)
|
||||
#define MAX_IMM15 ((int) 0x7fff)
|
||||
|
||||
#endif /* MICROBLAZE_OPC */
|
||||
|
||||
|
|
@ -407,8 +593,42 @@ char fsl_register_prefix[] = "rfsl";
|
|||
#define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW)
|
||||
#define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW)
|
||||
|
||||
/* Local function prototypes. */
|
||||
|
||||
static char * get_field (long instr, long mask, unsigned short low);
|
||||
static char * get_field_imm (long instr);
|
||||
static char * get_field_imm5 (long instr);
|
||||
static char * get_field_rfsl (long instr);
|
||||
static char * get_field_imm15 (long instr);
|
||||
#if 0
|
||||
static char * get_field_unsigned_imm (long instr);
|
||||
#endif
|
||||
char * get_field_special (long instr, struct op_code_struct * op);
|
||||
unsigned long read_insn_microblaze (bfd_vma memaddr,
|
||||
struct disassemble_info *info,
|
||||
struct op_code_struct **opr);
|
||||
enum microblaze_instr get_insn_microblaze (long inst,
|
||||
bfd_boolean *isunsignedimm,
|
||||
enum microblaze_instr_type *insn_type,
|
||||
short *delay_slots);
|
||||
short get_delay_slots_microblaze (long inst);
|
||||
enum microblaze_instr microblaze_decode_insn (long insn,
|
||||
int *rd,
|
||||
int *ra,
|
||||
int *rb,
|
||||
int *imm);
|
||||
unsigned long
|
||||
microblaze_get_target_address (long inst,
|
||||
bfd_boolean immfound,
|
||||
int immval,
|
||||
long pcval,
|
||||
long r1val,
|
||||
long r2val,
|
||||
bfd_boolean *targetvalid,
|
||||
bfd_boolean *unconditionalbranch);
|
||||
|
||||
static char *
|
||||
get_field (long instr, long mask, unsigned short low)
|
||||
get_field (long instr, long mask, unsigned short low)
|
||||
{
|
||||
char tmpstr[25];
|
||||
sprintf(tmpstr, "%s%d", register_prefix, (int)((instr & mask) >> low));
|
||||
|
|
@ -416,7 +636,7 @@ get_field (long instr, long mask, unsigned short low)
|
|||
}
|
||||
|
||||
static char *
|
||||
get_field_imm (long instr)
|
||||
get_field_imm (long instr)
|
||||
{
|
||||
char tmpstr[25];
|
||||
sprintf(tmpstr, "%d", (short)((instr & IMM_MASK) >> IMM_LOW));
|
||||
|
|
@ -424,7 +644,7 @@ get_field_imm (long instr)
|
|||
}
|
||||
|
||||
static char *
|
||||
get_field_imm5 (long instr)
|
||||
get_field_imm5 (long instr)
|
||||
{
|
||||
char tmpstr[25];
|
||||
sprintf(tmpstr, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
|
||||
|
|
@ -432,24 +652,24 @@ get_field_imm5 (long instr)
|
|||
}
|
||||
|
||||
static char *
|
||||
get_field_imm12 (long instr)
|
||||
get_field_rfsl (long instr)
|
||||
{
|
||||
char tmpstr[25];
|
||||
sprintf(tmpstr, "%s%d", fsl_register_prefix, (short)((instr & IMM12_MASK) >> IMM_LOW));
|
||||
sprintf(tmpstr, "%s%d", fsl_register_prefix, (short)((instr & RFSL_MASK) >> IMM_LOW));
|
||||
return(strdup(tmpstr));
|
||||
}
|
||||
|
||||
static char *
|
||||
get_field_imm14 (long instr)
|
||||
get_field_imm15 (long instr)
|
||||
{
|
||||
char tmpstr[25];
|
||||
sprintf(tmpstr, "%d", (short)((instr & IMM14_MASK) >> IMM_LOW));
|
||||
sprintf(tmpstr, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW));
|
||||
return(strdup(tmpstr));
|
||||
}
|
||||
|
||||
#if 0
|
||||
static char *
|
||||
get_field_unsigned_imm (long instr)
|
||||
get_field_unsigned_imm (long instr)
|
||||
{
|
||||
char tmpstr[25];
|
||||
sprintf(tmpstr, "%d", (int)((instr & IMM_MASK) >> IMM_LOW));
|
||||
|
|
@ -470,13 +690,14 @@ get_field_unsigned_imm (long instr)
|
|||
}
|
||||
*/
|
||||
|
||||
static char *
|
||||
get_field_special (long instr, struct op_code_struct * op)
|
||||
char *
|
||||
get_field_special (long instr, struct op_code_struct * op)
|
||||
{
|
||||
char tmpstr[25];
|
||||
char spr[5];
|
||||
char spr[6];
|
||||
|
||||
switch ( (((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) ) {
|
||||
|
||||
case REG_MSR_MASK :
|
||||
strcpy(spr, "msr");
|
||||
break;
|
||||
|
|
@ -491,19 +712,51 @@ get_field_special (long instr, struct op_code_struct * op)
|
|||
break;
|
||||
case REG_FSR_MASK :
|
||||
strcpy(spr, "fsr");
|
||||
break;
|
||||
default :
|
||||
strcpy(spr, "pc");
|
||||
break;
|
||||
case REG_BTR_MASK :
|
||||
strcpy(spr, "btr");
|
||||
break;
|
||||
case REG_EDR_MASK :
|
||||
strcpy(spr, "edr");
|
||||
break;
|
||||
case REG_PID_MASK :
|
||||
strcpy(spr, "pid");
|
||||
break;
|
||||
case REG_ZPR_MASK :
|
||||
strcpy(spr, "zpr");
|
||||
break;
|
||||
case REG_TLBX_MASK :
|
||||
strcpy(spr, "tlbx");
|
||||
break;
|
||||
case REG_TLBLO_MASK :
|
||||
strcpy(spr, "tlblo");
|
||||
break;
|
||||
case REG_TLBHI_MASK :
|
||||
strcpy(spr, "tlbhi");
|
||||
break;
|
||||
case REG_TLBSX_MASK :
|
||||
strcpy(spr, "tlbsx");
|
||||
break;
|
||||
default :
|
||||
{
|
||||
if ( ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000) == REG_PVR_MASK) {
|
||||
sprintf(tmpstr, "%spvr%d", register_prefix, (unsigned short)(((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) ^ REG_PVR_MASK);
|
||||
return(strdup(tmpstr));
|
||||
} else {
|
||||
strcpy(spr, "pc");
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
sprintf(tmpstr, "%s%s", register_prefix, spr);
|
||||
return(strdup(tmpstr));
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
read_insn_microblaze(bfd_vma memaddr, struct disassemble_info *info,
|
||||
struct op_code_struct ** opr)
|
||||
unsigned long
|
||||
read_insn_microblaze (bfd_vma memaddr,
|
||||
struct disassemble_info *info,
|
||||
struct op_code_struct **opr)
|
||||
{
|
||||
unsigned char ibytes[4];
|
||||
int status;
|
||||
|
|
@ -543,7 +796,7 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
|
|||
unsigned long inst, prev_inst;
|
||||
struct op_code_struct * op, *pop;
|
||||
int immval = 0;
|
||||
bfd_boolean immfound = false;
|
||||
bfd_boolean immfound = FALSE;
|
||||
static bfd_vma prev_insn_addr = -1; /*init the prev insn addr */
|
||||
static int prev_insn_vma = -1; /*init the prev insn vma */
|
||||
int curr_insn_vma = info->buffer_vma;
|
||||
|
|
@ -551,8 +804,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
|
|||
info->bytes_per_chunk = 4;
|
||||
|
||||
inst = read_insn_microblaze (memaddr, info, &op);
|
||||
if (inst == 0)
|
||||
if (inst == 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (prev_insn_vma == curr_insn_vma) {
|
||||
if (memaddr-(info->bytes_per_chunk) == prev_insn_addr) {
|
||||
|
|
@ -561,11 +815,11 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
|
|||
return -1;
|
||||
if (pop->instr == imm) {
|
||||
immval = (get_int_field_imm(prev_inst) << 16) & 0xffff0000;
|
||||
immfound = true;
|
||||
immfound = TRUE;
|
||||
}
|
||||
else {
|
||||
immval = 0;
|
||||
immfound = false;
|
||||
immfound = FALSE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -573,8 +827,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
|
|||
prev_insn_addr = memaddr;
|
||||
prev_insn_vma = curr_insn_vma;
|
||||
|
||||
if (op->name == 0)
|
||||
if (op->name == 0) {
|
||||
fprintf (stream, ".short 0x%04x", inst);
|
||||
}
|
||||
else
|
||||
{
|
||||
fprintf (stream, "%s", op->name);
|
||||
|
|
@ -603,11 +858,11 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
|
|||
case INST_TYPE_RD_R1_IMM5:
|
||||
fprintf(stream, "\t%s, %s, %s", get_field_rd(inst), get_field_r1(inst), get_field_imm5(inst));
|
||||
break;
|
||||
case INST_TYPE_RD_IMM12:
|
||||
fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_imm12(inst));
|
||||
case INST_TYPE_RD_RFSL:
|
||||
fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_rfsl(inst));
|
||||
break;
|
||||
case INST_TYPE_R1_IMM12:
|
||||
fprintf(stream, "\t%s, %s", get_field_r1(inst), get_field_imm12(inst));
|
||||
case INST_TYPE_R1_RFSL:
|
||||
fprintf(stream, "\t%s, %s", get_field_r1(inst), get_field_rfsl(inst));
|
||||
break;
|
||||
case INST_TYPE_RD_SPECIAL:
|
||||
fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_special(inst, op));
|
||||
|
|
@ -694,14 +949,16 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
|
|||
case INST_TYPE_RD_R1_SPECIAL:
|
||||
fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_r2(inst));
|
||||
break;
|
||||
case INST_TYPE_RD_IMM14:
|
||||
fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_imm14(inst));
|
||||
case INST_TYPE_RD_IMM15:
|
||||
fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_imm15(inst));
|
||||
break;
|
||||
/* For tuqula instruction */
|
||||
case INST_TYPE_RD:
|
||||
fprintf(stream, "\t%s", get_field_rd(inst));
|
||||
break;
|
||||
|
||||
case INST_TYPE_RFSL:
|
||||
fprintf(stream, "\t%s", get_field_rfsl(inst));
|
||||
break;
|
||||
default:
|
||||
/* if the disassembler lags the instruction set */
|
||||
fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
|
||||
|
|
@ -713,14 +970,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
|
|||
return 4;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static enum microblaze_instr
|
||||
get_insn_microblaze (long inst, boolean *isunsignedimm,
|
||||
enum microblaze_instr_type *insn_type,
|
||||
short *delay_slots )
|
||||
enum microblaze_instr
|
||||
get_insn_microblaze (long inst,
|
||||
bfd_boolean *isunsignedimm,
|
||||
enum microblaze_instr_type *insn_type,
|
||||
short *delay_slots)
|
||||
{
|
||||
struct op_code_struct * op;
|
||||
*isunsignedimm = false;
|
||||
*isunsignedimm = FALSE;
|
||||
|
||||
/* Just a linear search of the table. */
|
||||
for (op = opcodes; op->name != 0; op ++)
|
||||
|
|
@ -736,13 +993,11 @@ get_insn_microblaze (long inst, boolean *isunsignedimm,
|
|||
return op->instr;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
static short
|
||||
get_delay_slots_microblaze ( long inst )
|
||||
short
|
||||
get_delay_slots_microblaze (long inst)
|
||||
{
|
||||
boolean isunsignedimm;
|
||||
bfd_boolean isunsignedimm;
|
||||
enum microblaze_instr_type insn_type;
|
||||
enum microblaze_instr op;
|
||||
short delay_slots;
|
||||
|
|
@ -753,14 +1008,16 @@ get_delay_slots_microblaze ( long inst )
|
|||
else
|
||||
return delay_slots;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
static enum microblaze_instr
|
||||
microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *imm)
|
||||
enum microblaze_instr
|
||||
microblaze_decode_insn (long insn,
|
||||
int *rd,
|
||||
int *ra,
|
||||
int *rb,
|
||||
int *imm)
|
||||
{
|
||||
enum microblaze_instr op;
|
||||
boolean t1;
|
||||
bfd_boolean t1;
|
||||
enum microblaze_instr_type t2;
|
||||
short t3;
|
||||
|
||||
|
|
@ -772,40 +1029,42 @@ microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *imm)
|
|||
*imm = (int) t3;
|
||||
return (op);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
static unsigned long
|
||||
microblaze_get_target_address (long inst, boolean immfound, int immval,
|
||||
long pcval, long r1val, long r2val,
|
||||
boolean *targetvalid,
|
||||
boolean *unconditionalbranch)
|
||||
unsigned long
|
||||
microblaze_get_target_address (long inst,
|
||||
bfd_boolean immfound,
|
||||
int immval,
|
||||
long pcval,
|
||||
long r1val,
|
||||
long r2val,
|
||||
bfd_boolean *targetvalid,
|
||||
bfd_boolean *unconditionalbranch)
|
||||
{
|
||||
struct op_code_struct * op;
|
||||
long targetaddr = 0;
|
||||
|
||||
*unconditionalbranch = false;
|
||||
*unconditionalbranch = FALSE;
|
||||
/* Just a linear search of the table. */
|
||||
for (op = opcodes; op->name != 0; op ++)
|
||||
if (op->bit_sequence == (inst & op->opcode_mask))
|
||||
break;
|
||||
|
||||
if (op->name == 0) {
|
||||
*targetvalid = false;
|
||||
*targetvalid = FALSE;
|
||||
} else if (op->instr_type == branch_inst) {
|
||||
switch (op->inst_type) {
|
||||
case INST_TYPE_R2:
|
||||
*unconditionalbranch = true;
|
||||
*unconditionalbranch = TRUE;
|
||||
/* fallthru */
|
||||
case INST_TYPE_RD_R2:
|
||||
case INST_TYPE_R1_R2:
|
||||
targetaddr = r2val;
|
||||
*targetvalid = true;
|
||||
*targetvalid = TRUE;
|
||||
if (op->inst_offset_type == INST_PC_OFFSET)
|
||||
targetaddr += pcval;
|
||||
break;
|
||||
case INST_TYPE_IMM:
|
||||
*unconditionalbranch = true;
|
||||
*unconditionalbranch = TRUE;
|
||||
/* fallthru */
|
||||
case INST_TYPE_RD_IMM:
|
||||
case INST_TYPE_R1_IMM:
|
||||
|
|
@ -819,10 +1078,10 @@ microblaze_get_target_address (long inst, boolean immfound, int immval,
|
|||
}
|
||||
if (op->inst_offset_type == INST_PC_OFFSET)
|
||||
targetaddr += pcval;
|
||||
*targetvalid = true;
|
||||
*targetvalid = TRUE;
|
||||
break;
|
||||
default:
|
||||
*targetvalid = false;
|
||||
*targetvalid = FALSE;
|
||||
break;
|
||||
}
|
||||
} else if (op->instr_type == return_inst) {
|
||||
|
|
@ -835,10 +1094,9 @@ microblaze_get_target_address (long inst, boolean immfound, int immval,
|
|||
targetaddr |= 0xFFFF0000;
|
||||
}
|
||||
targetaddr += r1val;
|
||||
*targetvalid = true;
|
||||
*targetvalid = TRUE;
|
||||
} else {
|
||||
*targetvalid = false;
|
||||
*targetvalid = FALSE;
|
||||
}
|
||||
return targetaddr;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue