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intc/xilinx_intc: Don't clear level sens. IRQs without ACK 

For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (via
IAR or direct write to ISR with !MER(2)).

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
master
Peter Crosthwaite 2013-06-11 10:58:25 +10:00 committed by Edgar E. Iglesias
parent 37a011e9ba
commit 6327c221ff
1 changed files with 1 additions and 7 deletions
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8
hw/intc/xilinx_intc.c
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@ -135,13 +135,7 @@ static void irq_handler(void *opaque, int irq, int level)
return;
}
/* Update source flops. Don't clear unless level triggered.
Edge triggered interrupts only go away when explicitely acked to
the interrupt controller. */
if (!(p->c_kind_of_intr & (1 << irq)) || level) {
p->regs[R_ISR] &= ~(1 << irq);
p->regs[R_ISR] |= (level << irq);
}
p->regs[R_ISR] |= (level << irq);
update_irq(p);
}