mirror of https://github.com/proxmox/mirror_qemu
tcg/ppc: Improve unaligned load/store handling on 64-bit backend
Currently, we get to the slow path for any unaligned access in the backend, because we effectively preserve the bottom address bits below the alignment requirement when comparing with the TLB entry, so any non-0 bit there will cause the compare to fail. For the same number of instructions, we can instead add the access size - 1 to the address and stick to clearing all the bottom bits. That means that normal unaligned accesses will not fallback (the HW will handle them fine). Only when crossing a page boundary well we end up having a mismatch because we'll end up pointing to the next page which cannot possibly be in that same TLB entry. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1437455978.5809.2.camel@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>master
parent
8cc580f6a0
commit
68d45bb61c
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@ -1361,7 +1361,7 @@ static void * const qemu_st_helpers[16] = {
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in CR7, loads the addend of the TLB into R3, and returns the register
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in CR7, loads the addend of the TLB into R3, and returns the register
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containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
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containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
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static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits,
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static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
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TCGReg addrlo, TCGReg addrhi,
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TCGReg addrlo, TCGReg addrhi,
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int mem_index, bool is_read)
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int mem_index, bool is_read)
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{
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{
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@ -1371,6 +1371,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits,
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: offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
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: offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
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int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
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int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
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TCGReg base = TCG_AREG0;
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TCGReg base = TCG_AREG0;
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TCGMemOp s_bits = opc & MO_SIZE;
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/* Extract the page index, shifted into place for tlb index. */
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/* Extract the page index, shifted into place for tlb index. */
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if (TCG_TARGET_REG_BITS == 64) {
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if (TCG_TARGET_REG_BITS == 64) {
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@ -1422,17 +1423,37 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits,
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to minimize any load use delay. */
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to minimize any load use delay. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
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/* Clear the non-page, non-alignment bits from the address. */
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/* Clear the non-page, non-alignment bits from the address */
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if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
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if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
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/* We don't support unaligned accesses on 32-bits, preserve
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* the bottom bits and thus trigger a comparison failure on
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* unaligned accesses
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*/
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
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(32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
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(32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
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} else if (!s_bits) {
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} else if (s_bits) {
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tcg_out_rld(s, RLDICR, TCG_REG_R0, addrlo,
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/* > byte access, we need to handle alignment */
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0, 63 - TARGET_PAGE_BITS);
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if ((opc & MO_AMASK) == MO_ALIGN) {
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/* Alignment required by the front-end, same as 32-bits */
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tcg_out_rld(s, RLDICL, TCG_REG_R0, addrlo,
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64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
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tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
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} else {
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/* We support unaligned accesses, we need to make sure we fail
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* if we cross a page boundary. The trick is to add the
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* access_size-1 to the address before masking the low bits.
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* That will make the address overflow to the next page if we
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* cross a page boundary which will then force a mismatch of
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* the TLB compare since the next page cannot possibly be in
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* the same TLB index.
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*/
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tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, (1 << s_bits) - 1));
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tcg_out_rld(s, RLDICR, TCG_REG_R0, TCG_REG_R0,
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0, 63 - TARGET_PAGE_BITS);
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}
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} else {
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} else {
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tcg_out_rld(s, RLDICL, TCG_REG_R0, addrlo,
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/* Byte access, just chop off the bits below the page index */
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64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
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tcg_out_rld(s, RLDICR, TCG_REG_R0, addrlo, 0, 63 - TARGET_PAGE_BITS);
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tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
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}
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}
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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@ -1592,7 +1613,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
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#ifdef CONFIG_SOFTMMU
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#ifdef CONFIG_SOFTMMU
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mem_index = get_mmuidx(oi);
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mem_index = get_mmuidx(oi);
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addrlo = tcg_out_tlb_read(s, s_bits, addrlo, addrhi, mem_index, true);
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addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
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/* Load a pointer into the current opcode w/conditional branch-link. */
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/* Load a pointer into the current opcode w/conditional branch-link. */
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label_ptr = s->code_ptr;
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label_ptr = s->code_ptr;
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@ -1667,7 +1688,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
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#ifdef CONFIG_SOFTMMU
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#ifdef CONFIG_SOFTMMU
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mem_index = get_mmuidx(oi);
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mem_index = get_mmuidx(oi);
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addrlo = tcg_out_tlb_read(s, s_bits, addrlo, addrhi, mem_index, false);
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addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
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/* Load a pointer into the current opcode w/conditional branch-link. */
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/* Load a pointer into the current opcode w/conditional branch-link. */
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label_ptr = s->code_ptr;
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label_ptr = s->code_ptr;
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