mirror of https://github.com/proxmox/mirror_qemu
target-arm: A64: add support for 2-src shift reg insns
This adds 2-src variable shift register instructions: C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, use enums for shift types] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>master
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8220e911c2
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6c1adc919b
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@ -1077,6 +1077,20 @@ static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
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}
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}
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}
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}
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/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
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static void handle_shift_reg(DisasContext *s,
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enum a64_shift_type shift_type, unsigned int sf,
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unsigned int rm, unsigned int rn, unsigned int rd)
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{
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TCGv_i64 tcg_shift = tcg_temp_new_i64();
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TCGv_i64 tcg_rd = cpu_reg(s, rd);
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TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
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tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31);
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shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift);
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tcg_temp_free_i64(tcg_shift);
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}
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/* C3.5.8 Data-processing (2 source)
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/* C3.5.8 Data-processing (2 source)
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* 31 30 29 28 21 20 16 15 10 9 5 4 0
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* 31 30 29 28 21 20 16 15 10 9 5 4 0
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* +----+---+---+-----------------+------+--------+------+------+
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* +----+---+---+-----------------+------+--------+------+------+
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@ -1105,9 +1119,17 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
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handle_div(s, true, sf, rm, rn, rd);
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handle_div(s, true, sf, rm, rn, rd);
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break;
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break;
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case 8: /* LSLV */
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case 8: /* LSLV */
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handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
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break;
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case 9: /* LSRV */
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case 9: /* LSRV */
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handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd);
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break;
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case 10: /* ASRV */
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case 10: /* ASRV */
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handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd);
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break;
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case 11: /* RORV */
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case 11: /* RORV */
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handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd);
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break;
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case 16:
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case 16:
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case 17:
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case 17:
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case 18:
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case 18:
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