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target/arm: Convert T16 one low register and immediate 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-53-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Richard Henderson 2019-09-04 12:30:42 -07:00 committed by Peter Maydell
parent c4d3095bb6
commit 6c6d237a86
2 changed files with 13 additions and 42 deletions
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11
target/arm/t16.decode
View File

@ -133,3 +133,14 @@ SUB_rrri 0001101 ... ... ... @addsub_3
ADD_rri 0001 110 ... ... ... @addsub_2i
SUB_rri 0001 111 ... ... ... @addsub_2i
# Add, subtract, compare, move (one low register and immediate)
%reg_8 8:3
@arith_1i ..... rd:3 imm:8 \
&s_rri_rot rot=0 rn=%reg_8
MOV_rxi 00100 ... ........ @arith_1i %s
CMP_xri 00101 ... ........ @arith_1i s=1
ADD_rri 00110 ... ........ @arith_1i %s
SUB_rri 00111 ... ........ @arith_1i %s

44
target/arm/translate.c
View File

@ -10705,48 +10705,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
store_reg(s, rd, tmp);
}
break;
case 2: case 3:
/*
* 0b001x_xxxx_xxxx_xxxx
* - Add, subtract, compare, move (one low register and immediate)
*/
op = (insn >> 11) & 3;
rd = (insn >> 8) & 0x7;
if (op == 0) { /* mov */
tmp = tcg_temp_new_i32();
tcg_gen_movi_i32(tmp, insn & 0xff);
if (!s->condexec_mask)
gen_logic_CC(tmp);
store_reg(s, rd, tmp);
} else {
tmp = load_reg(s, rd);
tmp2 = tcg_temp_new_i32();
tcg_gen_movi_i32(tmp2, insn & 0xff);
switch (op) {
case 1: /* cmp */
gen_sub_CC(tmp, tmp, tmp2);
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(tmp2);
break;
case 2: /* add */
if (s->condexec_mask)
tcg_gen_add_i32(tmp, tmp, tmp2);
else
gen_add_CC(tmp, tmp, tmp2);
tcg_temp_free_i32(tmp2);
store_reg(s, rd, tmp);
break;
case 3: /* sub */
if (s->condexec_mask)
tcg_gen_sub_i32(tmp, tmp, tmp2);
else
gen_sub_CC(tmp, tmp, tmp2);
tcg_temp_free_i32(tmp2);
store_reg(s, rd, tmp);
break;
}
}
break;
case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
goto illegal_op;
case 4:
if (insn & (1 << 11)) {
rd = (insn >> 8) & 7;