mirror of https://github.com/proxmox/mirror_qemu
aspeed: add the definitions for the AST2400 A1 SoC
There is not much differences with the A0 revision apart from the DDR calibration. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-10-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
parent
74af4eec29
commit
6efbac908f
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@ -58,6 +58,16 @@ static const AspeedSoCInfo aspeed_socs[] = {
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.fmc_typename = "aspeed.smc.fmc",
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.fmc_typename = "aspeed.smc.fmc",
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.spi_typename = aspeed_soc_ast2400_typenames,
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.spi_typename = aspeed_soc_ast2400_typenames,
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}, {
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.name = "ast2400-a1",
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.cpu_model = "arm926",
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.silicon_rev = AST2400_A1_SILICON_REV,
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.sdram_base = AST2400_SDRAM_BASE,
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.sram_size = 0x8000,
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.spis_num = 1,
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.fmc_typename = "aspeed.smc.fmc",
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.spi_typename = aspeed_soc_ast2400_typenames,
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}, {
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}, {
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.name = "ast2400",
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.name = "ast2400",
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.cpu_model = "arm926",
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.cpu_model = "arm926",
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@ -231,6 +231,7 @@ static void aspeed_scu_reset(DeviceState *dev)
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switch (s->silicon_rev) {
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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reset = ast2400_a0_resets;
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reset = ast2400_a0_resets;
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break;
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break;
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case AST2500_A0_SILICON_REV:
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case AST2500_A0_SILICON_REV:
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@ -249,6 +250,7 @@ static void aspeed_scu_reset(DeviceState *dev)
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static uint32_t aspeed_silicon_revs[] = {
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static uint32_t aspeed_silicon_revs[] = {
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AST2400_A0_SILICON_REV,
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AST2400_A0_SILICON_REV,
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AST2400_A1_SILICON_REV,
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AST2500_A0_SILICON_REV,
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AST2500_A0_SILICON_REV,
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AST2500_A1_SILICON_REV,
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AST2500_A1_SILICON_REV,
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};
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};
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@ -119,6 +119,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
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/* Make sure readonly bits are kept */
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/* Make sure readonly bits are kept */
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switch (s->silicon_rev) {
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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data &= ~ASPEED_SDMC_READONLY_MASK;
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data &= ~ASPEED_SDMC_READONLY_MASK;
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break;
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break;
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case AST2500_A0_SILICON_REV:
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case AST2500_A0_SILICON_REV:
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@ -193,6 +194,7 @@ static void aspeed_sdmc_reset(DeviceState *dev)
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/* Set ram size bit and defaults values */
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/* Set ram size bit and defaults values */
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switch (s->silicon_rev) {
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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s->regs[R_CONF] |=
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s->regs[R_CONF] |=
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ASPEED_SDMC_VGA_COMPAT |
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ASPEED_SDMC_VGA_COMPAT |
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ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
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ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
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@ -224,6 +226,7 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
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switch (s->silicon_rev) {
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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s->ram_bits = ast2400_rambits(s);
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s->ram_bits = ast2400_rambits(s);
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break;
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break;
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case AST2500_A0_SILICON_REV:
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case AST2500_A0_SILICON_REV:
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@ -32,6 +32,7 @@ typedef struct AspeedSCUState {
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} AspeedSCUState;
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} AspeedSCUState;
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#define AST2400_A0_SILICON_REV 0x02000303U
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#define AST2400_A0_SILICON_REV 0x02000303U
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#define AST2400_A1_SILICON_REV 0x02010303U
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#define AST2500_A0_SILICON_REV 0x04000303U
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#define AST2500_A0_SILICON_REV 0x04000303U
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#define AST2500_A1_SILICON_REV 0x04010303U
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#define AST2500_A1_SILICON_REV 0x04010303U
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