mirror of https://github.com/proxmox/mirror_qemu
target-mips: fix EntryHi.EHINV being cleared on TLB exception
While implementing TLB invalidation feature we forgot to modify part of code responsible for updating EntryHi during TLB exception. Consequently EntryHi.EHINV is unexpectedly cleared on the exception. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>master
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7f81dbb9a0
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701074a6fc
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@ -396,6 +396,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
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env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
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((address >> 9) & 0x007ffff0);
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env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
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(env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
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(address & (TARGET_PAGE_MASK << 1));
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#if defined(TARGET_MIPS64)
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env->CP0_EntryHi &= env->SEGMask;
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