mirror of https://github.com/proxmox/mirror_qemu
target/arm: Allow SVE to be disabled via a CPU property
Since 97a28b0eea
("target/arm: Allow VFP and Neon to be disabled via
a CPU property") we can disable the 'max' cpu model's VFP and neon
features, but there's no way to disable SVE. Add the 'sve=on|off'
property to give it that flexibility. We also rename
cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them
to follow the typical *_get/set_<property-name> pattern.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-4-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
parent
bd31b751a3
commit
73234775ad
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@ -200,7 +200,8 @@ static void arm_cpu_reset(CPUState *s)
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env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
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env->cp15.cptr_el[3] |= CPTR_EZ;
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/* with maximum vector length */
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env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
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env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
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cpu->sve_max_vq - 1 : 0;
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env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
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env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
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/*
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@ -256,14 +256,22 @@ static void aarch64_a72_initfn(Object *obj)
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
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static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
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uint32_t value;
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/* All vector lengths are disabled when SVE is off. */
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if (!cpu_isar_feature(aa64_sve, cpu)) {
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value = 0;
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} else {
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value = cpu->sve_max_vq;
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}
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visit_type_uint32(v, name, &value, errp);
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}
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static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
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static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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@ -279,6 +287,34 @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
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error_propagate(errp, err);
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}
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static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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bool value = cpu_isar_feature(aa64_sve, cpu);
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visit_type_bool(v, name, &value, errp);
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}
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static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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Error *err = NULL;
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bool value;
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uint64_t t;
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visit_type_bool(v, name, &value, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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t = cpu->isar.id_aa64pfr0;
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t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
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cpu->isar.id_aa64pfr0 = t;
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}
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/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
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* otherwise, a CPU with as many features enabled as our emulation supports.
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* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
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@ -391,8 +427,10 @@ static void aarch64_max_initfn(Object *obj)
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#endif
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cpu->sve_max_vq = ARM_MAX_VQ;
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object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
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cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
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object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
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cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
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object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
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cpu_arm_set_sve, NULL, NULL, &error_fatal);
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}
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}
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@ -97,7 +97,7 @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
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* then the order that considers those dependencies must be used.
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*/
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static const char *cpu_model_advertised_features[] = {
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"aarch64", "pmu",
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"aarch64", "pmu", "sve",
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NULL
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};
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@ -197,6 +197,7 @@ static void test_query_cpu_model_expansion(const void *data)
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if (g_str_equal(qtest_get_arch(), "aarch64")) {
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assert_has_feature(qts, "max", "aarch64");
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assert_has_feature(qts, "max", "sve");
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assert_has_feature(qts, "cortex-a57", "pmu");
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assert_has_feature(qts, "cortex-a57", "aarch64");
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