mirror of https://github.com/proxmox/mirror_qemu
target-arm: A64: Implement SHLL, SHLL2
Implement the SHLL and SHLL2 instructions from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-9-git-send-email-peter.maydell@linaro.orgmaster
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@ -8529,6 +8529,36 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
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}
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}
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}
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}
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static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
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{
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/* Implement SHLL and SHLL2 */
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int pass;
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int part = is_q ? 2 : 0;
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TCGv_i64 tcg_res[2];
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for (pass = 0; pass < 2; pass++) {
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static NeonGenWidenFn * const widenfns[3] = {
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gen_helper_neon_widen_u8,
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gen_helper_neon_widen_u16,
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tcg_gen_extu_i32_i64,
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};
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NeonGenWidenFn *widenfn = widenfns[size];
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TCGv_i32 tcg_op = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32);
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tcg_res[pass] = tcg_temp_new_i64();
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widenfn(tcg_res[pass], tcg_op);
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tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size);
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tcg_temp_free_i32(tcg_op);
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}
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for (pass = 0; pass < 2; pass++) {
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write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
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tcg_temp_free_i64(tcg_res[pass]);
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}
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}
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/* C3.6.17 AdvSIMD two reg misc
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/* C3.6.17 AdvSIMD two reg misc
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
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* +---+---+---+-----------+------+-----------+--------+-----+------+------+
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* +---+---+---+-----------+------+-----------+--------+-----+------+------+
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@ -8590,7 +8620,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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unallocated_encoding(s);
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unallocated_encoding(s);
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return;
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return;
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}
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}
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unsupported_encoding(s, insn);
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handle_shll(s, is_q, size, rn, rd);
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return;
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return;
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case 0xa: /* CMLT */
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case 0xa: /* CMLT */
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if (u == 1) {
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if (u == 1) {
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