mirror of https://github.com/proxmox/mirror_qemu
tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
While there are no specific 16-bit rotate instructions, there are double-word shifts, which can perform the same operation. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>master
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965d5d0681
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786c7ef3b7
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@ -3444,6 +3444,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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case INDEX_op_rotlv_vec:
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case INDEX_op_rotlv_vec:
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case INDEX_op_rotrv_vec:
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case INDEX_op_rotrv_vec:
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switch (vece) {
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switch (vece) {
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case MO_16:
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return have_avx512vbmi2 ? -1 : 0;
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case MO_32:
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case MO_32:
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case MO_64:
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case MO_64:
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return have_avx512vl ? 1 : have_avx2 ? -1 : 0;
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return have_avx512vl ? 1 : have_avx2 ? -1 : 0;
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@ -3588,6 +3590,12 @@ static void expand_vec_rotli(TCGType type, unsigned vece,
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return;
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return;
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}
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}
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if (have_avx512vbmi2) {
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vec_gen_4(INDEX_op_x86_vpshldi_vec, type, vece,
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tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v1), imm);
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return;
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}
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t = tcg_temp_new_vec(type);
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t = tcg_temp_new_vec(type);
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tcg_gen_shli_vec(vece, t, v1, imm);
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tcg_gen_shli_vec(vece, t, v1, imm);
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tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm);
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tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm);
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@ -3618,8 +3626,16 @@ static void expand_vec_rotls(TCGType type, unsigned vece,
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static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
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static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
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TCGv_vec v1, TCGv_vec sh, bool right)
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TCGv_vec v1, TCGv_vec sh, bool right)
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{
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{
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TCGv_vec t = tcg_temp_new_vec(type);
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TCGv_vec t;
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if (have_avx512vbmi2) {
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vec_gen_4(right ? INDEX_op_x86_vpshrdv_vec : INDEX_op_x86_vpshldv_vec,
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type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1),
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tcgv_vec_arg(v1), tcgv_vec_arg(sh));
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return;
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}
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t = tcg_temp_new_vec(type);
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tcg_gen_dupi_vec(vece, t, 8 << vece);
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tcg_gen_dupi_vec(vece, t, 8 << vece);
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tcg_gen_sub_vec(vece, t, t, sh);
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tcg_gen_sub_vec(vece, t, t, sh);
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if (right) {
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if (right) {
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