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ARM: fix CPS masks (Vincent Palatin). 

According to ARM Reference Manual (DDI0100 A4.1.16),
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162
master
balrog 2008-07-19 10:34:35 +00:00
parent 22478e79f2
commit 7997d92f2c
1 changed files with 2 additions and 2 deletions
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4
target-arm/translate.c
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@ -5813,7 +5813,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
/* Coprocessor double register transfer. */
} else if ((insn & 0x0f000010) == 0x0e000010) {
/* Additional coprocessor register transfer. */
} else if ((insn & 0x0ff10010) == 0x01000000) {
} else if ((insn & 0x0ff10020) == 0x01000000) {
uint32_t mask;
uint32_t val;
/* cps (privileged) */
@ -5830,7 +5830,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
if (insn & (1 << 18))
val |= mask;
}
if (insn & (1 << 14)) {
if (insn & (1 << 17)) {
mask |= CPSR_M;
val |= (insn & 0x1f);
}