mirror of https://github.com/proxmox/mirror_qemu
target/arm: Add is_secure parameter to do_ats_write
Use get_phys_addr_with_secure directly. For a-profile, this is the one place where the value of is_secure may not equal arm_is_secure(env). Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221001162318.153420-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
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03bea66e7f
commit
7aee3cb956
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@ -3191,7 +3191,8 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
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#ifdef CONFIG_TCG
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#ifdef CONFIG_TCG
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static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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MMUAccessType access_type, ARMMMUIdx mmu_idx)
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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bool is_secure)
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{
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{
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bool ret;
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bool ret;
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uint64_t par64;
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uint64_t par64;
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@ -3199,7 +3200,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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ARMMMUFaultInfo fi = {};
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ARMMMUFaultInfo fi = {};
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GetPhysAddrResult res = {};
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GetPhysAddrResult res = {};
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ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi);
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ret = get_phys_addr_with_secure(env, value, access_type, mmu_idx,
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is_secure, &res, &fi);
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/*
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/*
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* ATS operations only do S1 or S1+S2 translations, so we never
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* ATS operations only do S1 or S1+S2 translations, so we never
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@ -3371,6 +3373,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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switch (el) {
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switch (el) {
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case 3:
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case 3:
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mmu_idx = ARMMMUIdx_SE3;
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mmu_idx = ARMMMUIdx_SE3;
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secure = true;
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break;
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break;
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case 2:
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case 2:
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g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
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g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
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@ -3392,6 +3395,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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switch (el) {
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switch (el) {
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case 3:
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case 3:
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mmu_idx = ARMMMUIdx_SE10_0;
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mmu_idx = ARMMMUIdx_SE10_0;
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secure = true;
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break;
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break;
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case 2:
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case 2:
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g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
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g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
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@ -3407,16 +3411,18 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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case 4:
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case 4:
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/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
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/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
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mmu_idx = ARMMMUIdx_E10_1;
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mmu_idx = ARMMMUIdx_E10_1;
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secure = false;
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break;
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break;
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case 6:
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case 6:
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/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
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/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
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mmu_idx = ARMMMUIdx_E10_0;
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mmu_idx = ARMMMUIdx_E10_0;
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secure = false;
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break;
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break;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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}
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}
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par64 = do_ats_write(env, value, access_type, mmu_idx);
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par64 = do_ats_write(env, value, access_type, mmu_idx, secure);
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A32_BANKED_CURRENT_REG_SET(env, par, par64);
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A32_BANKED_CURRENT_REG_SET(env, par, par64);
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#else
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#else
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@ -3432,7 +3438,8 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
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MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
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MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
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uint64_t par64;
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uint64_t par64;
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par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
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/* There is no SecureEL2 for AArch32. */
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par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, false);
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A32_BANKED_CURRENT_REG_SET(env, par, par64);
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A32_BANKED_CURRENT_REG_SET(env, par, par64);
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#else
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#else
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@ -3475,6 +3482,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
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break;
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break;
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case 6: /* AT S1E3R, AT S1E3W */
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case 6: /* AT S1E3R, AT S1E3W */
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mmu_idx = ARMMMUIdx_SE3;
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mmu_idx = ARMMMUIdx_SE3;
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secure = true;
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break;
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break;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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@ -3493,7 +3501,8 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
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g_assert_not_reached();
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g_assert_not_reached();
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}
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}
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env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
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env->cp15.par_el[1] = do_ats_write(env, value, access_type,
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mmu_idx, secure);
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#else
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#else
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/* Handled by hardware accelerator. */
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/* Handled by hardware accelerator. */
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g_assert_not_reached();
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g_assert_not_reached();
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