mirror of https://github.com/proxmox/mirror_qemu
tests/tcg: i386: extend BMI test
Cover all BMI1 and BMI2 instructions, both 32- and 64-bit. Due to the use of inlines, the test now has to be compiled with -O2. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>master
Paolo Bonzini
parent
9e8504c057
commit
7b764d4173
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@ -18,6 +18,7 @@ test-i386-pcmpistri: CFLAGS += -msse4.2
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run-test-i386-pcmpistri: QEMU_OPTS += -cpu max
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run-plugin-test-i386-pcmpistri-%: QEMU_OPTS += -cpu max
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test-i386-bmi2: CFLAGS=-O2
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run-test-i386-bmi2: QEMU_OPTS += -cpu max
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run-plugin-test-i386-bmi2-%: QEMU_OPTS += -cpu max
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@ -1,6 +1,66 @@
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/* See if various BMI2 instructions give expected results */
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#include <assert.h>
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#include <stdint.h>
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#include <stdio.h>
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#define insn1q(name, arg0) \
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static inline uint64_t name##q(uint64_t arg0) \
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{ \
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uint64_t result64; \
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asm volatile (#name "q %1, %0" : "=r"(result64) : "rm"(arg0)); \
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return result64; \
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}
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#define insn1l(name, arg0) \
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static inline uint32_t name##l(uint32_t arg0) \
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{ \
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uint32_t result32; \
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asm volatile (#name "l %k1, %k0" : "=r"(result32) : "rm"(arg0)); \
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return result32; \
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}
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#define insn2q(name, arg0, c0, arg1, c1) \
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static inline uint64_t name##q(uint64_t arg0, uint64_t arg1) \
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{ \
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uint64_t result64; \
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asm volatile (#name "q %2, %1, %0" : "=r"(result64) : c0(arg0), c1(arg1)); \
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return result64; \
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}
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#define insn2l(name, arg0, c0, arg1, c1) \
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static inline uint32_t name##l(uint32_t arg0, uint32_t arg1) \
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{ \
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uint32_t result32; \
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asm volatile (#name "l %k2, %k1, %k0" : "=r"(result32) : c0(arg0), c1(arg1)); \
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return result32; \
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}
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#ifdef __x86_64
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insn2q(pext, src, "r", mask, "rm")
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insn2q(pdep, src, "r", mask, "rm")
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insn2q(andn, clear, "rm", val, "r")
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insn2q(bextr, range, "rm", val, "r")
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insn2q(bzhi, pos, "rm", val, "r")
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insn2q(rorx, val, "r", n, "i")
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insn2q(sarx, val, "rm", n, "r")
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insn2q(shlx, val, "rm", n, "r")
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insn2q(shrx, val, "rm", n, "r")
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insn1q(blsi, src)
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insn1q(blsmsk, src)
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insn1q(blsr, src)
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#endif
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insn2l(pext, src, "r", mask, "rm")
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insn2l(pdep, src, "r", mask, "rm")
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insn2l(andn, clear, "rm", val, "r")
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insn2l(bextr, range, "rm", val, "r")
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insn2l(bzhi, pos, "rm", val, "r")
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insn2l(rorx, val, "r", n, "i")
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insn2l(sarx, val, "rm", n, "r")
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insn2l(shlx, val, "rm", n, "r")
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insn2l(shrx, val, "rm", n, "r")
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insn1l(blsi, src)
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insn1l(blsmsk, src)
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insn1l(blsr, src)
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int main(int argc, char *argv[]) {
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uint64_t ehlo = 0x202020204f4c4845ull;
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@ -11,32 +71,125 @@ int main(int argc, char *argv[]) {
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uint64_t result64;
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/* 64 bits */
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asm volatile ("pextq %2, %1, %0" : "=r"(result64) : "r"(ehlo), "m"(mask));
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result64 = andnq(mask, ehlo);
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assert(result64 == 0x002020204d4c4844);
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result64 = pextq(ehlo, mask);
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assert(result64 == 133);
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asm volatile ("pdepq %2, %1, %0" : "=r"(result64) : "r"(result64), "m"(mask));
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result64 = pdepq(result64, mask);
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assert(result64 == (ehlo & mask));
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asm volatile ("pextq %2, %1, %0" : "=r"(result64) : "r"(-1ull), "m"(mask));
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result64 = pextq(-1ull, mask);
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assert(result64 == 511); /* mask has 9 bits set */
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asm volatile ("pdepq %2, %1, %0" : "=r"(result64) : "r"(-1ull), "m"(mask));
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result64 = pdepq(-1ull, mask);
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assert(result64 == mask);
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result64 = bextrq(mask, 0x3f00);
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assert(result64 == (mask & ~INT64_MIN));
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result64 = bextrq(mask, 0x1038);
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assert(result64 == 0xa0);
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result64 = bextrq(mask, 0x10f8);
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assert(result64 == 0);
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result64 = blsiq(0x30);
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assert(result64 == 0x10);
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result64 = blsiq(0x30ull << 32);
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assert(result64 == 0x10ull << 32);
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result64 = blsmskq(0x30);
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assert(result64 == 0x1f);
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result64 = blsrq(0x30);
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assert(result64 == 0x20);
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result64 = blsrq(0x30ull << 32);
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assert(result64 == 0x20ull << 32);
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result64 = bzhiq(mask, 0x3f);
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assert(result64 == (mask & ~INT64_MIN));
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result64 = bzhiq(mask, 0x1f);
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assert(result64 == (mask & ~(-1 << 30)));
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result64 = rorxq(0x2132435465768798, 8);
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assert(result64 == 0x9821324354657687);
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result64 = sarxq(0xffeeddccbbaa9988, 8);
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assert(result64 == 0xffffeeddccbbaa99);
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result64 = sarxq(0x77eeddccbbaa9988, 8 | 64);
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assert(result64 == 0x0077eeddccbbaa99);
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result64 = shrxq(0xffeeddccbbaa9988, 8);
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assert(result64 == 0x00ffeeddccbbaa99);
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result64 = shrxq(0x77eeddccbbaa9988, 8 | 192);
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assert(result64 == 0x0077eeddccbbaa99);
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result64 = shlxq(0xffeeddccbbaa9988, 8);
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assert(result64 == 0xeeddccbbaa998800);
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#endif
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/* 32 bits */
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asm volatile ("pextl %2, %k1, %k0" : "=r"(result32) : "r"((uint32_t) ehlo), "m"(mask));
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result32 = andnl(mask, ehlo);
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assert(result32 == 0x04d4c4844);
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result32 = pextl((uint32_t) ehlo, mask);
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assert(result32 == 5);
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asm volatile ("pdepl %2, %k1, %k0" : "=r"(result32) : "r"(result32), "m"(mask));
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result32 = pdepl(result32, mask);
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assert(result32 == (uint32_t)(ehlo & mask));
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asm volatile ("pextl %2, %k1, %k0" : "=r"(result32) : "r"(-1ull), "m"(mask));
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result32 = pextl(-1u, mask);
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assert(result32 == 7); /* mask has 3 bits set */
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asm volatile ("pdepl %2, %k1, %k0" : "=r"(result32) : "r"(-1ull), "m"(mask));
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result32 = pdepl(-1u, mask);
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assert(result32 == (uint32_t)mask);
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result32 = bextrl(mask, 0x1f00);
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assert(result32 == (mask & ~INT32_MIN));
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result32 = bextrl(ehlo, 0x1018);
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assert(result32 == 0x4f);
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result32 = bextrl(mask, 0x1038);
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assert(result32 == 0);
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result32 = blsil(0xffff);
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assert(result32 == 1);
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result32 = blsmskl(0x300);
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assert(result32 == 0x1ff);
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result32 = blsrl(0xffc);
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assert(result32 == 0xff8);
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result32 = bzhil(mask, 0xf);
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assert(result32 == 1);
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result32 = rorxl(0x65768798, 8);
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assert(result32 == 0x98657687);
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result32 = sarxl(0xffeeddcc, 8);
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assert(result32 == 0xffffeedd);
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result32 = sarxl(0x77eeddcc, 8 | 32);
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assert(result32 == 0x0077eedd);
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result32 = shrxl(0xffeeddcc, 8);
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assert(result32 == 0x00ffeedd);
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result32 = shrxl(0x77eeddcc, 8 | 128);
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assert(result32 == 0x0077eedd);
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result32 = shlxl(0xffeeddcc, 8);
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assert(result32 == 0xeeddcc00);
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return 0;
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}
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