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target/ppc: Put dbcr0 single-step bits into hflags 

Because these bits were not in hflags, the code generated
for single-stepping on BookE was essentially random.
Recompute hflags when storing to dbcr0.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-5-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
master
Richard Henderson 2021-03-23 12:43:34 -06:00 committed by David Gibson
parent 26c55599b8
commit 7da31f260d
3 changed files with 20 additions and 18 deletions
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24
target/ppc/helper_regs.c
View File

@ -114,13 +114,23 @@ void hreg_compute_hflags(CPUPPCState *env)
hflags |= le << MSR_LE;
}
if (ppc_flags & POWERPC_FLAG_BE) {
QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
msr_mask |= 1 << MSR_BE;
}
if (ppc_flags & POWERPC_FLAG_SE) {
QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
msr_mask |= 1 << MSR_SE;
if (ppc_flags & POWERPC_FLAG_DE) {
target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
if (dbcr0 & DBCR0_ICMP) {
hflags |= 1 << HFLAGS_SE;
}
if (dbcr0 & DBCR0_BRT) {
hflags |= 1 << HFLAGS_BE;
}
} else {
if (ppc_flags & POWERPC_FLAG_BE) {
QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
msr_mask |= 1 << MSR_BE;
}
if (ppc_flags & POWERPC_FLAG_SE) {
QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
msr_mask |= 1 << MSR_SE;
}
}
if (msr_is_64bit(env, msr)) {

3
target/ppc/misc_helper.c
View File

@ -215,6 +215,9 @@ void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
{
/* Bits 26 & 27 affect single-stepping. */
hreg_compute_hflags(env);
/* Bits 28 & 29 affect reset or shutdown. */
store_40x_dbcr0(env, val);
}

11
target/ppc/translate.c
View File

@ -7923,17 +7923,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
if ((hflags >> HFLAGS_BE) & 1) {
ctx->singlestep_enabled |= CPU_BRANCH_STEP;
}
if ((env->flags & POWERPC_FLAG_DE) && msr_de) {
ctx->singlestep_enabled = 0;
target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
if (dbcr0 & DBCR0_ICMP) {
ctx->singlestep_enabled |= CPU_SINGLE_STEP;
}
if (dbcr0 & DBCR0_BRT) {
ctx->singlestep_enabled |= CPU_BRANCH_STEP;
}
}
if (unlikely(ctx->base.singlestep_enabled)) {
ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
}