mirror of https://github.com/proxmox/mirror_qemu
Merge with balrog@git.sv.gnu.org:/srv/git/qemu.git
commit
7ef6e71c59
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@ -485,9 +485,6 @@ int cpu_exec(CPUState *env1)
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env->exception_index = env->interrupt_index;
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env->exception_index = env->interrupt_index;
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do_interrupt(env);
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do_interrupt(env);
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env->interrupt_index = 0;
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env->interrupt_index = 0;
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#if !defined(CONFIG_USER_ONLY)
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cpu_check_irqs(env);
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#endif
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next_tb = 0;
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next_tb = 0;
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}
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}
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} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
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} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
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@ -60,13 +60,13 @@
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#define dh_retvar_decl0_void void
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#define dh_retvar_decl0_void void
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#define dh_retvar_decl0_i32 TCGv_i32 retval
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#define dh_retvar_decl0_i32 TCGv_i32 retval
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#define dh_retvar_decl0_i64 TCGv_i64 retval
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#define dh_retvar_decl0_i64 TCGv_i64 retval
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#define dh_retvar_decl0_ptr TCGv_iptr retval
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#define dh_retvar_decl0_ptr TCGv_ptr retval
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#define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t))
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#define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t))
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#define dh_retvar_decl_void
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#define dh_retvar_decl_void
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#define dh_retvar_decl_i32 TCGv_i32 retval,
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#define dh_retvar_decl_i32 TCGv_i32 retval,
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#define dh_retvar_decl_i64 TCGv_i64 retval,
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#define dh_retvar_decl_i64 TCGv_i64 retval,
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#define dh_retvar_decl_ptr TCGv_iptr retval,
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#define dh_retvar_decl_ptr TCGv_ptr retval,
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#define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t))
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#define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t))
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#define dh_retvar_void TCG_CALL_DUMMY_ARG
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#define dh_retvar_void TCG_CALL_DUMMY_ARG
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16
hw/esp.c
16
hw/esp.c
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@ -115,7 +115,9 @@ struct ESPState {
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#define CMD_TI 0x10
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#define CMD_TI 0x10
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#define CMD_ICCS 0x11
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#define CMD_ICCS 0x11
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#define CMD_MSGACC 0x12
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#define CMD_MSGACC 0x12
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#define CMD_PAD 0x18
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#define CMD_SATN 0x1a
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#define CMD_SATN 0x1a
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#define CMD_SEL 0x41
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#define CMD_SELATN 0x42
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#define CMD_SELATN 0x42
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#define CMD_SELATNS 0x43
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#define CMD_SELATNS 0x43
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#define CMD_ENSEL 0x44
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#define CMD_ENSEL 0x44
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@ -530,15 +532,25 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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s->rregs[ESP_RINTR] = INTR_DC;
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s->rregs[ESP_RINTR] = INTR_DC;
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s->rregs[ESP_RSEQ] = 0;
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s->rregs[ESP_RSEQ] = 0;
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break;
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break;
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case CMD_PAD:
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DPRINTF("Transfer padding (%2.2x)\n", val);
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s->rregs[ESP_RSTAT] = STAT_TC;
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s->rregs[ESP_RINTR] = INTR_FC;
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s->rregs[ESP_RSEQ] = 0;
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break;
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case CMD_SATN:
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case CMD_SATN:
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DPRINTF("Set ATN (%2.2x)\n", val);
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DPRINTF("Set ATN (%2.2x)\n", val);
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break;
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break;
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case CMD_SEL:
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DPRINTF("Select without ATN (%2.2x)\n", val);
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handle_satn(s);
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break;
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case CMD_SELATN:
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case CMD_SELATN:
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DPRINTF("Set ATN (%2.2x)\n", val);
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DPRINTF("Select with ATN (%2.2x)\n", val);
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handle_satn(s);
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handle_satn(s);
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break;
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break;
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case CMD_SELATNS:
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case CMD_SELATNS:
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DPRINTF("Set ATN & stop (%2.2x)\n", val);
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DPRINTF("Select with ATN & stop (%2.2x)\n", val);
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handle_satn_stop(s);
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handle_satn_stop(s);
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break;
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break;
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case CMD_ENSEL:
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case CMD_ENSEL:
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@ -125,9 +125,8 @@ static PCIDevice *qemu_pci_hot_add_storage(Monitor *mon,
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monitor_printf(mon, "Parameter addr not supported\n");
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monitor_printf(mon, "Parameter addr not supported\n");
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return NULL;
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return NULL;
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}
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}
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} else if (type == IF_VIRTIO) {
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} else {
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monitor_printf(mon, "virtio requires a backing file/device.\n");
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dinfo = NULL;
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return NULL;
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}
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}
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switch (type) {
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switch (type) {
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@ -135,6 +134,10 @@ static PCIDevice *qemu_pci_hot_add_storage(Monitor *mon,
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dev = pci_create("lsi53c895a", devaddr);
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dev = pci_create("lsi53c895a", devaddr);
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break;
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break;
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case IF_VIRTIO:
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case IF_VIRTIO:
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if (!dinfo) {
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monitor_printf(mon, "virtio requires a backing file/device.\n");
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return NULL;
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}
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dev = pci_create("virtio-blk-pci", devaddr);
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dev = pci_create("virtio-blk-pci", devaddr);
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qdev_prop_set_drive(&dev->qdev, "drive", dinfo);
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qdev_prop_set_drive(&dev->qdev, "drive", dinfo);
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break;
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break;
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@ -220,11 +220,14 @@ static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
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slavio_intctlm_mem_writel,
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slavio_intctlm_mem_writel,
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};
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};
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void slavio_pic_info(Monitor *mon, void *opaque)
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void slavio_pic_info(Monitor *mon, DeviceState *dev)
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{
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{
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SLAVIO_INTCTLState *s = opaque;
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SysBusDevice *sd;
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SLAVIO_INTCTLState *s;
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int i;
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int i;
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sd = sysbus_from_qdev(dev);
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s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
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for (i = 0; i < MAX_CPUS; i++) {
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for (i = 0; i < MAX_CPUS; i++) {
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monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
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monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
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s->slaves[i].intreg_pending);
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s->slaves[i].intreg_pending);
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@ -233,15 +236,18 @@ void slavio_pic_info(Monitor *mon, void *opaque)
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s->intregm_pending, s->intregm_disabled);
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s->intregm_pending, s->intregm_disabled);
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}
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}
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void slavio_irq_info(Monitor *mon, void *opaque)
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void slavio_irq_info(Monitor *mon, DeviceState *dev)
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{
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{
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#ifndef DEBUG_IRQ_COUNT
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#ifndef DEBUG_IRQ_COUNT
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monitor_printf(mon, "irq statistic code not compiled.\n");
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monitor_printf(mon, "irq statistic code not compiled.\n");
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#else
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#else
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SLAVIO_INTCTLState *s = opaque;
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SysBusDevice *sd;
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SLAVIO_INTCTLState *s;
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int i;
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int i;
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int64_t count;
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int64_t count;
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sd = sysbus_from_qdev(dev);
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s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
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monitor_printf(mon, "IRQ statistics:\n");
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monitor_printf(mon, "IRQ statistics:\n");
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for (i = 0; i < 32; i++) {
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for (i = 0; i < 32; i++) {
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count = s->irq_count[i];
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count = s->irq_count[i];
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15
hw/sun4m.c
15
hw/sun4m.c
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@ -209,7 +209,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
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m48t59_write(nvram, i, image[i]);
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m48t59_write(nvram, i, image[i]);
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}
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}
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static void *slavio_intctl;
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static DeviceState *slavio_intctl;
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void pic_info(Monitor *mon)
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void pic_info(Monitor *mon)
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{
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{
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@ -748,7 +748,6 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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unsigned long kernel_size;
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unsigned long kernel_size;
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BlockDriverState *fd[MAX_FD];
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BlockDriverState *fd[MAX_FD];
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void *fw_cfg;
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void *fw_cfg;
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DeviceState *dev;
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DriveInfo *dinfo;
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DriveInfo *dinfo;
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/* init CPUs */
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/* init CPUs */
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@ -768,16 +767,16 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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prom_init(hwdef->slavio_base, bios_name);
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prom_init(hwdef->slavio_base, bios_name);
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dev = slavio_intctl_init(hwdef->intctl_base,
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slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
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hwdef->intctl_base + 0x10000ULL,
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hwdef->intctl_base + 0x10000ULL,
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cpu_irqs,
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cpu_irqs,
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7);
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7);
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for (i = 0; i < 32; i++) {
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for (i = 0; i < 32; i++) {
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slavio_irq[i] = qdev_get_gpio_in(dev, i);
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slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
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}
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}
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for (i = 0; i < MAX_CPUS; i++) {
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for (i = 0; i < MAX_CPUS; i++) {
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slavio_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
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slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
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}
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}
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if (hwdef->idreg_base) {
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if (hwdef->idreg_base) {
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@ -23,8 +23,8 @@ static inline void sparc_iommu_memory_write(void *opaque,
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}
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}
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/* slavio_intctl.c */
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/* slavio_intctl.c */
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void slavio_pic_info(Monitor *mon, void *opaque);
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void slavio_pic_info(Monitor *mon, DeviceState *dev);
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void slavio_irq_info(Monitor *mon, void *opaque);
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void slavio_irq_info(Monitor *mon, DeviceState *dev);
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/* sun4c_intctl.c */
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/* sun4c_intctl.c */
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void sun4c_pic_info(Monitor *mon, void *opaque);
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void sun4c_pic_info(Monitor *mon, void *opaque);
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@ -439,6 +439,22 @@ int cpu_sparc_exec(CPUSPARCState *s);
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#endif
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#endif
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#ifndef NO_CPU_IO_DEFS
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#ifndef NO_CPU_IO_DEFS
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static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
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{
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if (unlikely(cwp >= env1->nwindows))
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cwp -= env1->nwindows;
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return cwp;
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}
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static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
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{
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if (unlikely(cwp < 0))
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cwp += env1->nwindows;
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return cwp;
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}
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#endif
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|
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static inline void memcpy32(target_ulong *dst, const target_ulong *src)
|
static inline void memcpy32(target_ulong *dst, const target_ulong *src)
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{
|
{
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dst[0] = src[0];
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dst[0] = src[0];
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@ -463,43 +479,25 @@ static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
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env1->regwptr = env1->regbase + (new_cwp * 16);
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env1->regwptr = env1->regbase + (new_cwp * 16);
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}
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}
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|
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static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
|
/* sun4m.c, sun4u.c */
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{
|
void cpu_check_irqs(CPUSPARCState *env);
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if (unlikely(cwp >= env1->nwindows))
|
|
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cwp -= env1->nwindows;
|
|
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return cwp;
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|
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}
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|
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static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
|
static inline void PUT_PSR(CPUSPARCState *env1, target_ulong val)
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{
|
{
|
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if (unlikely(cwp < 0))
|
env1->psr = val & PSR_ICC;
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cwp += env1->nwindows;
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env1->psref = (val & PSR_EF)? 1 : 0;
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return cwp;
|
env1->psrpil = (val & PSR_PIL) >> 8;
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}
|
#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
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|
cpu_check_irqs(env1);
|
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#endif
|
#endif
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|
env1->psrs = (val & PSR_S)? 1 : 0;
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|
env1->psrps = (val & PSR_PS)? 1 : 0;
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#if !defined (TARGET_SPARC64)
|
#if !defined (TARGET_SPARC64)
|
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#define PUT_PSR(env, val) do { int _tmp = val; \
|
env1->psret = (val & PSR_ET)? 1 : 0;
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env->psr = _tmp & PSR_ICC; \
|
|
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env->psref = (_tmp & PSR_EF)? 1 : 0; \
|
|
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env->psrpil = (_tmp & PSR_PIL) >> 8; \
|
|
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env->psrs = (_tmp & PSR_S)? 1 : 0; \
|
|
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env->psrps = (_tmp & PSR_PS)? 1 : 0; \
|
|
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env->psret = (_tmp & PSR_ET)? 1 : 0; \
|
|
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cpu_set_cwp(env, _tmp & PSR_CWP); \
|
|
||||||
CC_OP = CC_OP_FLAGS; \
|
|
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} while (0)
|
|
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#else
|
|
||||||
#define PUT_PSR(env, val) do { int _tmp = val; \
|
|
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env->psr = _tmp & PSR_ICC; \
|
|
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env->psref = (_tmp & PSR_EF)? 1 : 0; \
|
|
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env->psrpil = (_tmp & PSR_PIL) >> 8; \
|
|
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env->psrs = (_tmp & PSR_S)? 1 : 0; \
|
|
||||||
env->psrps = (_tmp & PSR_PS)? 1 : 0; \
|
|
||||||
cpu_set_cwp(env, _tmp & PSR_CWP); \
|
|
||||||
CC_OP = CC_OP_FLAGS; \
|
|
||||||
} while (0)
|
|
||||||
#endif
|
#endif
|
||||||
|
cpu_set_cwp(env1, val & PSR_CWP);
|
||||||
|
env1->cc_op = CC_OP_FLAGS;
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef TARGET_SPARC64
|
#ifdef TARGET_SPARC64
|
||||||
#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
|
#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
|
||||||
|
@ -585,9 +583,6 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
|
||||||
#include "cpu-all.h"
|
#include "cpu-all.h"
|
||||||
#include "exec-all.h"
|
#include "exec-all.h"
|
||||||
|
|
||||||
/* sum4m.c, sun4u.c */
|
|
||||||
void cpu_check_irqs(CPUSPARCState *env);
|
|
||||||
|
|
||||||
#ifdef TARGET_SPARC64
|
#ifdef TARGET_SPARC64
|
||||||
/* sun4u.c */
|
/* sun4u.c */
|
||||||
void cpu_tick_set_count(void *opaque, uint64_t count);
|
void cpu_tick_set_count(void *opaque, uint64_t count);
|
||||||
|
|
|
@ -1134,6 +1134,7 @@ static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
|
||||||
} else {
|
} else {
|
||||||
dc->pc = dc->npc;
|
dc->pc = dc->npc;
|
||||||
dc->npc = target;
|
dc->npc = target;
|
||||||
|
tcg_gen_mov_tl(cpu_pc, cpu_npc);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
flush_cond(dc, r_cond);
|
flush_cond(dc, r_cond);
|
||||||
|
@ -1174,6 +1175,7 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
|
||||||
} else {
|
} else {
|
||||||
dc->pc = dc->npc;
|
dc->pc = dc->npc;
|
||||||
dc->npc = target;
|
dc->npc = target;
|
||||||
|
tcg_gen_mov_tl(cpu_pc, cpu_npc);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
flush_cond(dc, r_cond);
|
flush_cond(dc, r_cond);
|
||||||
|
|
Loading…
Reference in New Issue