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mirror_qemu
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target-arm queue: 

* raspi: add model of cprman clock manager
  * sbsa-ref: add an SBSA generic watchdog device
  * arm/trace: Fix hex printing
  * raspi: Add models of Pi 3 model A+, Pi Zero and Pi A+
  * hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly
  * Nuvoton NPCM7xx: Add USB, RNG, GPIO and watchdog support
  * hw/arm: fix min_cpus for xlnx-versal-virt platform
  * hw/arm/highbank: Silence warnings about missing fallthrough statements
  * linux-user: Support Aarch64 BTI
  * Armv7M systick: fix corner case bugs by rewriting to use ptimer
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201027-1' into staging

target-arm queue:
 * raspi: add model of cprman clock manager
 * sbsa-ref: add an SBSA generic watchdog device
 * arm/trace: Fix hex printing
 * raspi: Add models of Pi 3 model A+, Pi Zero and Pi A+
 * hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly
 * Nuvoton NPCM7xx: Add USB, RNG, GPIO and watchdog support
 * hw/arm: fix min_cpus for xlnx-versal-virt platform
 * hw/arm/highbank: Silence warnings about missing fallthrough statements
 * linux-user: Support Aarch64 BTI
 * Armv7M systick: fix corner case bugs by rewriting to use ptimer

# gpg: Signature made Tue 27 Oct 2020 11:27:10 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20201027-1: (48 commits)
  hw/timer/armv7m_systick: Rewrite to use ptimers
  hw/core/ptimer: Support ptimer being disabled by timer callback
  hw/arm/sbsa-ref: add SBSA watchdog device
  hw/watchdog: Implement SBSA watchdog device
  hw/arm/bcm2835_peripherals: connect the UART clock
  hw/char/pl011: add a clock input
  hw/misc/bcm2835_cprman: add sane reset values to the registers
  hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
  hw/misc/bcm2835_cprman: implement clock mux behaviour
  hw/misc/bcm2835_cprman: add a clock mux skeleton implementation
  hw/misc/bcm2835_cprman: implement PLL channels behaviour
  hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation
  hw/misc/bcm2835_cprman: implement PLLs behaviour
  hw/misc/bcm2835_cprman: add a PLL skeleton implementation
  hw/arm/raspi: add a skeleton implementation of the CPRMAN
  hw/arm/raspi: fix CPRMAN base address
  hw/core/clock: trace clock values in Hz instead of ns
  hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro
  arm/trace: Fix hex printing
  hw/arm/raspi: Add the Raspberry Pi 3 model A+
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Peter Maydell 2020-10-29 11:40:04 +00:00
parent c044400914 32bd322a01
commit 802427bcda
64 changed files with 5461 additions and 279 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -755,6 +755,7 @@ L: qemu-arm@nongnu.org
S: Supported
F: hw/*/npcm7xx*
F: include/hw/*/npcm7xx*
F: tests/qtest/npcm7xx*
F: pc-bios/npcm7xx_bootrom.bin
F: roms/vbootrom

6
docs/system/arm/nuvoton.rst
View File

@ -38,11 +38,13 @@ Supported devices
* DDR4 memory controller (dummy interface indicating memory training is done)
* OTP controllers (no protection features)
* Flash Interface Unit (FIU; no protection features)
* Random Number Generator (RNG)
* USB host (USBH)
* GPIO controller
Missing devices
---------------
* GPIO controller
* LPC/eSPI host-to-BMC interface, including
* Keyboard and mouse controller interface (KBCI)
@ -53,13 +55,11 @@ Missing devices
* eSPI slave interface
* Ethernet controllers (GMAC and EMC)
* USB host (USBH)
* USB device (USBD)
* SMBus controller (SMBF)
* Peripheral SPI controller (PSPI)
* Analog to Digital Converter (ADC)
* SD/MMC host
* Random Number Generator (RNG)
* PECI interface
* Pulse Width Modulation (PWM)
* Tachometer

1
hw/arm/Kconfig
View File

@ -212,6 +212,7 @@ config SBSA_REF
select PL031 # RTC
select PL061 # GPIO
select USB_EHCI_SYSBUS
select WDT_SBSA
config SABRELITE
bool

15
hw/arm/bcm2835_peripherals.c
View File

@ -121,6 +121,9 @@ static void bcm2835_peripherals_init(Object *obj)
/* DWC2 */
object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB);
/* CPRMAN clock manager */
object_initialize_child(obj, "cprman", &s->cprman, TYPE_BCM2835_CPRMAN);
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
OBJECT(&s->gpu_bus_mr));
}
@ -160,6 +163,15 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
return;
}
/* CPRMAN clock manager */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) {
return;
}
memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0));
qdev_connect_clock_in(DEVICE(&s->uart0), "clk",
qdev_get_clock_out(DEVICE(&s->cprman), "uart-out"));
memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0));
sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
@ -354,8 +366,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);

182
hw/arm/bcm2836.c
View File

@ -17,46 +17,45 @@
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
struct BCM283XInfo {
typedef struct BCM283XClass {
/*< private >*/
DeviceClass parent_class;
/*< public >*/
const char *name;
const char *cpu_type;
unsigned core_count;
hwaddr peri_base; /* Peripheral base address seen by the CPU */
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
int clusterid;
};
} BCM283XClass;
static const BCM283XInfo bcm283x_socs[] = {
{
.name = TYPE_BCM2836,
.cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"),
.peri_base = 0x3f000000,
.ctrl_base = 0x40000000,
.clusterid = 0xf,
},
#ifdef TARGET_AARCH64
{
.name = TYPE_BCM2837,
.cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
.peri_base = 0x3f000000,
.ctrl_base = 0x40000000,
.clusterid = 0x0,
},
#endif
};
#define BCM283X_CLASS(klass) \
OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
#define BCM283X_GET_CLASS(obj) \
OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
static Property bcm2836_enabled_cores_property =
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
static void bcm2836_init(Object *obj)
{
BCM283XState *s = BCM283X(obj);
BCM283XClass *bc = BCM283X_GET_CLASS(obj);
const BCM283XInfo *info = bc->info;
int n;
for (n = 0; n < BCM283X_NCPUS; n++) {
for (n = 0; n < bc->core_count; n++) {
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
info->cpu_type);
bc->cpu_type);
}
if (bc->core_count > 1) {
qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
}
object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
if (bc->ctrl_base) {
object_initialize_child(obj, "control", &s->control,
TYPE_BCM2836_CONTROL);
}
object_initialize_child(obj, "peripherals", &s->peripherals,
TYPE_BCM2835_PERIPHERALS);
@ -66,13 +65,11 @@ static void bcm2836_init(Object *obj)
"vcram-size");
}
static void bcm2836_realize(DeviceState *dev, Error **errp)
static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
BCM283XClass *bc = BCM283X_GET_CLASS(dev);
const BCM283XInfo *info = bc->info;
Object *obj;
int n;
/* common peripherals from bcm2835 */
@ -81,21 +78,52 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
return;
return false;
}
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
"sd-bus");
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
info->peri_base, 1);
bc->peri_base, 1);
return true;
}
static void bcm2835_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
if (!bcm283x_common_realize(dev, errp)) {
return;
}
if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
return;
}
/* Connect irq/fiq outputs from the interrupt controller. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
}
static void bcm2836_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
BCM283XClass *bc = BCM283X_GET_CLASS(dev);
int n;
if (!bcm283x_common_realize(dev, errp)) {
return;
}
/* bcm2836 interrupt controller (and mailboxes, etc.) */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
@ -104,11 +132,11 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
for (n = 0; n < BCM283X_NCPUS; n++) {
/* TODO: this should be converted to a property of ARM_CPU */
s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n;
s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;
/* set periphbase/CBAR value for CPU-local registers */
if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
info->peri_base, errp)) {
bc->peri_base, errp)) {
return;
}
@ -142,47 +170,77 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
}
}
static Property bcm2836_props[] = {
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
BCM283X_NCPUS),
DEFINE_PROP_END_OF_LIST()
};
static void bcm283x_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->info = data;
dc->realize = bcm2836_realize;
device_class_set_props(dc, bcm2836_props);
/* Reason: Must be wired up in code (see raspi_init() function) */
dc->user_creatable = false;
}
static const TypeInfo bcm283x_type_info = {
.name = TYPE_BCM283X,
.parent = TYPE_DEVICE,
.instance_size = sizeof(BCM283XState),
.instance_init = bcm2836_init,
.class_size = sizeof(BCM283XClass),
.abstract = true,
static void bcm2835_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
bc->core_count = 1;
bc->peri_base = 0x20000000;
dc->realize = bcm2835_realize;
};
static void bcm2836_register_types(void)
static void bcm2836_class_init(ObjectClass *oc, void *data)
{
int i;
DeviceClass *dc = DEVICE_CLASS(oc);
BCM283XClass *bc = BCM283X_CLASS(oc);
type_register_static(&bcm283x_type_info);
for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
TypeInfo ti = {
.name = bcm283x_socs[i].name,
.parent = TYPE_BCM283X,
.class_init = bcm283x_class_init,
.class_data = (void *) &bcm283x_socs[i],
};
type_register(&ti);
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
bc->core_count = BCM283X_NCPUS;
bc->peri_base = 0x3f000000;
bc->ctrl_base = 0x40000000;
bc->clusterid = 0xf;
dc->realize = bcm2836_realize;
};
#ifdef TARGET_AARCH64
static void bcm2837_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
bc->core_count = BCM283X_NCPUS;
bc->peri_base = 0x3f000000;
bc->ctrl_base = 0x40000000;
bc->clusterid = 0x0;
dc->realize = bcm2836_realize;
};
#endif
static const TypeInfo bcm283x_types[] = {
{
.name = TYPE_BCM2835,
.parent = TYPE_BCM283X,
.class_init = bcm2835_class_init,
}, {
.name = TYPE_BCM2836,
.parent = TYPE_BCM283X,
.class_init = bcm2836_class_init,
#ifdef TARGET_AARCH64
}, {
.name = TYPE_BCM2837,
.parent = TYPE_BCM283X,
.class_init = bcm2837_class_init,
#endif
}, {
.name = TYPE_BCM283X,
.parent = TYPE_DEVICE,
.instance_size = sizeof(BCM283XState),
.instance_init = bcm2836_init,
.class_size = sizeof(BCM283XClass),
.class_init = bcm283x_class_init,
.abstract = true,
}
}
};
type_init(bcm2836_register_types)
DEFINE_TYPES(bcm283x_types)

2
hw/arm/highbank.c
View File

@ -92,10 +92,12 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
address_space_stl_notdirty(&address_space_memory,
SMP_BOOT_REG + 0x30, 0,
MEMTXATTRS_UNSPECIFIED, NULL);
/* fallthrough */
case 3:
address_space_stl_notdirty(&address_space_memory,
SMP_BOOT_REG + 0x20, 0,
MEMTXATTRS_UNSPECIFIED, NULL);
/* fallthrough */
case 2:
address_space_stl_notdirty(&address_space_memory,
SMP_BOOT_REG + 0x10, 0,

126
hw/arm/npcm7xx.c
View File

@ -44,6 +44,11 @@
#define NPCM7XX_GCR_BA (0xf0800000)
#define NPCM7XX_CLK_BA (0xf0801000)
#define NPCM7XX_MC_BA (0xf0824000)
#define NPCM7XX_RNG_BA (0xf000b000)
/* USB Host modules */
#define NPCM7XX_EHCI_BA (0xf0806000)
#define NPCM7XX_OHCI_BA (0xf0807000)
/* Internal AHB SRAM */
#define NPCM7XX_RAM3_BA (0xc0008000)
@ -86,6 +91,19 @@ enum NPCM7xxInterrupt {
NPCM7XX_TIMER12_IRQ,
NPCM7XX_TIMER13_IRQ,
NPCM7XX_TIMER14_IRQ,
NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
NPCM7XX_EHCI_IRQ = 61,
NPCM7XX_OHCI_IRQ = 62,
NPCM7XX_GPIO0_IRQ = 116,
NPCM7XX_GPIO1_IRQ,
NPCM7XX_GPIO2_IRQ,
NPCM7XX_GPIO3_IRQ,
NPCM7XX_GPIO4_IRQ,
NPCM7XX_GPIO5_IRQ,
NPCM7XX_GPIO6_IRQ,
NPCM7XX_GPIO7_IRQ,
};
/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
@ -120,6 +138,55 @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
0xb8000000, /* CS3 */
};
static const struct {
hwaddr regs_addr;
uint32_t unconnected_pins;
uint32_t reset_pu;
uint32_t reset_pd;
uint32_t reset_osrc;
uint32_t reset_odsc;
} npcm7xx_gpio[] = {
{
.regs_addr = 0xf0010000,
.reset_pu = 0xff03ffff,
.reset_pd = 0x00fc0000,
}, {
.regs_addr = 0xf0011000,
.unconnected_pins = 0x0000001e,
.reset_pu = 0xfefffe07,
.reset_pd = 0x010001e0,
}, {
.regs_addr = 0xf0012000,
.reset_pu = 0x780fffff,
.reset_pd = 0x07f00000,
.reset_odsc = 0x00700000,
}, {
.regs_addr = 0xf0013000,
.reset_pu = 0x00fc0000,
.reset_pd = 0xff000000,
}, {
.regs_addr = 0xf0014000,
.reset_pu = 0xffffffff,
}, {
.regs_addr = 0xf0015000,
.reset_pu = 0xbf83f801,
.reset_pd = 0x007c0000,
.reset_osrc = 0x000000f1,
.reset_odsc = 0x3f9f80f1,
}, {
.regs_addr = 0xf0016000,
.reset_pu = 0xfc00f801,
.reset_pd = 0x000007fe,
.reset_odsc = 0x00000800,
}, {
.regs_addr = 0xf0017000,
.unconnected_pins = 0xffffff00,
.reset_pu = 0x0000007f,
.reset_osrc = 0x0000007f,
.reset_odsc = 0x0000007f,
},
};
static const struct {
const char *name;
hwaddr regs_addr;
@ -253,11 +320,19 @@ static void npcm7xx_init(Object *obj)
object_initialize_child(obj, "otp2", &s->fuse_array,
TYPE_NPCM7XX_FUSE_ARRAY);
object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
}
for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
}
object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
@ -353,6 +428,15 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
qemu_irq irq = npcm7xx_irq(s, first_irq + j);
sysbus_connect_irq(sbd, j, irq);
}
/* IRQ for watchdogs */
sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
/* GPIO that connects clk module with watchdog */
qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
qdev_get_gpio_in_named(DEVICE(&s->clk),
NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
}
/* UART0..3 (16550 compatible) */
@ -362,6 +446,45 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
serial_hd(i), DEVICE_LITTLE_ENDIAN);
}
/* Random Number Generator. Cannot fail. */
sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
/* GPIO modules. Cannot fail. */
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio));
for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
Object *obj = OBJECT(&s->gpio[i]);
object_property_set_uint(obj, "reset-pullup",
npcm7xx_gpio[i].reset_pu, &error_abort);
object_property_set_uint(obj, "reset-pulldown",
npcm7xx_gpio[i].reset_pd, &error_abort);
object_property_set_uint(obj, "reset-osrc",
npcm7xx_gpio[i].reset_osrc, &error_abort);
object_property_set_uint(obj, "reset-odsc",
npcm7xx_gpio[i].reset_odsc, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr);
sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i));
}
/* USB Host */
object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0,
npcm7xx_irq(s, NPCM7XX_EHCI_IRQ));
object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0",
&error_abort);
object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
/*
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
* specified, but this is a programming error.
@ -400,7 +523,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
create_unimplemented_device("npcm7xx.rng", 0xf000b000, 4 * KiB);
create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
@ -447,8 +569,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
create_unimplemented_device("npcm7xx.ehci", 0xf0806000, 4 * KiB);
create_unimplemented_device("npcm7xx.ohci", 0xf0807000, 4 * KiB);
create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);

41
hw/arm/raspi.c
View File

@ -70,6 +70,7 @@ FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
FIELD(REV_CODE, STYLE, 23, 1);
typedef enum RaspiProcessorId {
PROCESSOR_ID_BCM2835 = 0,
PROCESSOR_ID_BCM2836 = 1,
PROCESSOR_ID_BCM2837 = 2,
} RaspiProcessorId;
@ -78,6 +79,7 @@ static const struct {
const char *type;
int cores_count;
} soc_property[] = {
[PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1},
[PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
[PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
};
@ -317,6 +319,24 @@ static void raspi_machine_class_common_init(MachineClass *mc,
mc->default_ram_id = "ram";
};
static void raspi0_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
rmc->board_rev = 0x920092; /* Revision 1.2 */
raspi_machine_class_common_init(mc, rmc->board_rev);
};
static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
rmc->board_rev = 0x900021; /* Revision 1.1 */
raspi_machine_class_common_init(mc, rmc->board_rev);
};
static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@ -328,6 +348,15 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
};
#ifdef TARGET_AARCH64
static void raspi3ap_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
rmc->board_rev = 0x9020e0; /* Revision 1.0 */
raspi_machine_class_common_init(mc, rmc->board_rev);
};
static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@ -341,10 +370,22 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
static const TypeInfo raspi_machine_types[] = {
{
.name = MACHINE_TYPE_NAME("raspi0"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi0_machine_class_init,
}, {
.name = MACHINE_TYPE_NAME("raspi1ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi1ap_machine_class_init,
}, {
.name = MACHINE_TYPE_NAME("raspi2b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
#ifdef TARGET_AARCH64
}, {
.name = MACHINE_TYPE_NAME("raspi3ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3ap_machine_class_init,
}, {
.name = MACHINE_TYPE_NAME("raspi3b"),
.parent = TYPE_RASPI_MACHINE,

23
hw/arm/sbsa-ref.c
View File

@ -40,6 +40,7 @@
#include "hw/qdev-properties.h"
#include "hw/usb.h"
#include "hw/char/pl011.h"
#include "hw/watchdog/sbsa_gwdt.h"
#include "net/net.h"
#include "qom/object.h"
@ -64,6 +65,9 @@ enum {
SBSA_GIC_DIST,
SBSA_GIC_REDIST,
SBSA_SECURE_EC,
SBSA_GWDT,
SBSA_GWDT_REFRESH,
SBSA_GWDT_CONTROL,
SBSA_SMMU,
SBSA_UART,
SBSA_RTC,
@ -104,6 +108,8 @@ static const MemMapEntry sbsa_ref_memmap[] = {
[SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
[SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
[SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
[SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
[SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
[SBSA_UART] = { 0x60000000, 0x00001000 },
[SBSA_RTC] = { 0x60010000, 0x00001000 },
[SBSA_GPIO] = { 0x60020000, 0x00001000 },
@ -134,6 +140,7 @@ static const int sbsa_ref_irqmap[] = {
[SBSA_AHCI] = 10,
[SBSA_EHCI] = 11,
[SBSA_SMMU] = 12, /* ... to 15 */
[SBSA_GWDT] = 16,
};
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
@ -448,6 +455,20 @@ static void create_rtc(const SBSAMachineState *sms)
sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
}
static void create_wdt(const SBSAMachineState *sms)
{
hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base;
hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base;
DeviceState *dev = qdev_new(TYPE_WDT_SBSA);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
int irq = sbsa_ref_irqmap[SBSA_GWDT];
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, rbase);
sysbus_mmio_map(s, 1, cbase);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
}
static DeviceState *gpio_key_dev;
static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
{
@ -731,6 +752,8 @@ static void sbsa_ref_init(MachineState *machine)
create_rtc(sms);
create_wdt(sms);
create_gpio(sms);
create_ahci(sms);

1
hw/arm/smmuv3.c
View File

@ -1440,6 +1440,7 @@ static const VMStateDescription vmstate_smmuv3 = {
.name = "smmuv3",
.version_id = 1,
.minimum_version_id = 1,
.priority = MIG_PRI_IOMMU,
.fields = (VMStateField[]) {
VMSTATE_UINT32(features, SMMUv3State),
VMSTATE_UINT8(sid_size, SMMUv3State),

2
hw/arm/trace-events
View File

@ -41,7 +41,7 @@ smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
smmuv3_decode_cd(uint32_t oas) "oas=%d"
smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d"
smmuv3_cmdq_cfgi_ste(int streamid) "streamid =%d"
smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"
smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"
smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"

1
hw/arm/xlnx-versal-virt.c
View File

@ -561,6 +561,7 @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
mc->desc = "Xilinx Versal Virtual development board";
mc->init = versal_virt_init;
mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
mc->no_cdrom = true;

45
hw/char/pl011.c
View File

@ -22,6 +22,7 @@
#include "hw/char/pl011.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "hw/qdev-clock.h"
#include "migration/vmstate.h"
#include "chardev/char-fe.h"
#include "qemu/log.h"
@ -169,6 +170,25 @@ static void pl011_set_read_trigger(PL011State *s)
s->read_trigger = 1;
}
static unsigned int pl011_get_baudrate(const PL011State *s)
{
uint64_t clk;
if (s->fbrd == 0) {
return 0;
}
clk = clock_get_hz(s->clk);
return (clk / ((s->ibrd << 6) + s->fbrd)) << 2;
}
static void pl011_trace_baudrate_change(const PL011State *s)
{
trace_pl011_baudrate_change(pl011_get_baudrate(s),
clock_get_hz(s->clk),
s->ibrd, s->fbrd);
}
static void pl011_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
@ -198,9 +218,11 @@ static void pl011_write(void *opaque, hwaddr offset,
break;
case 9: /* UARTIBRD */
s->ibrd = value;
pl011_trace_baudrate_change(s);
break;
case 10: /* UARTFBRD */
s->fbrd = value;
pl011_trace_baudrate_change(s);
break;
case 11: /* UARTLCR_H */
/* Reset the FIFO state on FIFO enable or disable */
@ -286,12 +308,29 @@ static void pl011_event(void *opaque, QEMUChrEvent event)
pl011_put_fifo(opaque, 0x400);
}
static void pl011_clock_update(void *opaque)
{
PL011State *s = PL011(opaque);
pl011_trace_baudrate_change(s);
}
static const MemoryRegionOps pl011_ops = {
.read = pl011_read,
.write = pl011_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_pl011_clock = {
.name = "pl011/clock",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_CLOCK(clk, PL011State),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_pl011 = {
.name = "pl011",
.version_id = 2,
@ -314,6 +353,10 @@ static const VMStateDescription vmstate_pl011 = {
VMSTATE_INT32(read_count, PL011State),
VMSTATE_INT32(read_trigger, PL011State),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * []) {
&vmstate_pl011_clock,
NULL
}
};
@ -334,6 +377,8 @@ static void pl011_init(Object *obj)
sysbus_init_irq(sbd, &s->irq[i]);
}
s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s);
s->read_trigger = 1;
s->ifl = 0x12;
s->cr = 0x300;

1
hw/char/trace-events
View File

@ -65,6 +65,7 @@ pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d"
pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d"
pl011_put_fifo_full(void) "FIFO now full, RXFF set"
pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")"
# cmsdk-apb-uart.c
cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

6
hw/core/clock.c
View File

@ -54,8 +54,8 @@ bool clock_set(Clock *clk, uint64_t period)
if (clk->period == period) {
return false;
}
trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
CLOCK_PERIOD_TO_NS(period));
trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period),
CLOCK_PERIOD_TO_HZ(period));
clk->period = period;
return true;
@ -69,7 +69,7 @@ static void clock_propagate_period(Clock *clk, bool call_callbacks)
if (child->period != clk->period) {
child->period = clk->period;
trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
CLOCK_PERIOD_TO_NS(clk->period),
CLOCK_PERIOD_TO_HZ(clk->period),
call_callbacks);
if (call_callbacks && child->callback) {
child->callback(child->callback_opaque);

4
hw/core/ptimer.c
View File

@ -117,6 +117,10 @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
}
if (delta == 0) {
if (s->enabled == 0) {
/* trigger callback disabled the timer already */
return;
}
if (!qtest_enabled()) {
fprintf(stderr, "Timer with delta zero, disabling\n");
}

4
hw/core/trace-events
View File

@ -31,6 +31,6 @@ resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)"
# clock.c
clock_set_source(const char *clk, const char *src) "'%s', src='%s'"
clock_disconnect(const char *clk) "'%s'"
clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', ns=%"PRIu64"->%"PRIu64
clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', %"PRIu64"Hz->%"PRIu64"Hz"
clock_propagate(const char *clk) "'%s'"
clock_update(const char *clk, const char *src, uint64_t val, int cb) "'%s', src='%s', ns=%"PRIu64", cb=%d"
clock_update(const char *clk, const char *src, uint64_t hz, int cb) "'%s', src='%s', val=%"PRIu64"Hz cb=%d"

1
hw/gpio/meson.build
View File

@ -6,6 +6,7 @@ softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c'))
softmmu_ss.add(when: 'CONFIG_ZAURUS', if_true: files('zaurus.c'))
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_gpio.c'))
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_gpio.c'))
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))

424
hw/gpio/npcm7xx_gpio.c Normal file
View File

@ -0,0 +1,424 @@
/*
* Nuvoton NPCM7xx General Purpose Input / Output (GPIO)
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "qemu/osdep.h"
#include "hw/gpio/npcm7xx_gpio.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/units.h"
#include "trace.h"
/* 32-bit register indices. */
enum NPCM7xxGPIORegister {
NPCM7XX_GPIO_TLOCK1,
NPCM7XX_GPIO_DIN,
NPCM7XX_GPIO_POL,
NPCM7XX_GPIO_DOUT,
NPCM7XX_GPIO_OE,
NPCM7XX_GPIO_OTYP,
NPCM7XX_GPIO_MP,
NPCM7XX_GPIO_PU,
NPCM7XX_GPIO_PD,
NPCM7XX_GPIO_DBNC,
NPCM7XX_GPIO_EVTYP,
NPCM7XX_GPIO_EVBE,
NPCM7XX_GPIO_OBL0,
NPCM7XX_GPIO_OBL1,
NPCM7XX_GPIO_OBL2,
NPCM7XX_GPIO_OBL3,
NPCM7XX_GPIO_EVEN,
NPCM7XX_GPIO_EVENS,
NPCM7XX_GPIO_EVENC,
NPCM7XX_GPIO_EVST,
NPCM7XX_GPIO_SPLCK,
NPCM7XX_GPIO_MPLCK,
NPCM7XX_GPIO_IEM,
NPCM7XX_GPIO_OSRC,
NPCM7XX_GPIO_ODSC,
NPCM7XX_GPIO_DOS = 0x68 / sizeof(uint32_t),
NPCM7XX_GPIO_DOC,
NPCM7XX_GPIO_OES,
NPCM7XX_GPIO_OEC,
NPCM7XX_GPIO_TLOCK2 = 0x7c / sizeof(uint32_t),
NPCM7XX_GPIO_REGS_END,
};
#define NPCM7XX_GPIO_REGS_SIZE (4 * KiB)
#define NPCM7XX_GPIO_LOCK_MAGIC1 (0xc0defa73)
#define NPCM7XX_GPIO_LOCK_MAGIC2 (0xc0de1248)
static void npcm7xx_gpio_update_events(NPCM7xxGPIOState *s, uint32_t din_diff)
{
uint32_t din_new = s->regs[NPCM7XX_GPIO_DIN];
/* Trigger on high level */
s->regs[NPCM7XX_GPIO_EVST] |= din_new & ~s->regs[NPCM7XX_GPIO_EVTYP];
/* Trigger on both edges */
s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & s->regs[NPCM7XX_GPIO_EVTYP]
& s->regs[NPCM7XX_GPIO_EVBE]);
/* Trigger on rising edge */
s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & din_new
& s->regs[NPCM7XX_GPIO_EVTYP]);
trace_npcm7xx_gpio_update_events(DEVICE(s)->canonical_path,
s->regs[NPCM7XX_GPIO_EVST],
s->regs[NPCM7XX_GPIO_EVEN]);
qemu_set_irq(s->irq, !!(s->regs[NPCM7XX_GPIO_EVST]
& s->regs[NPCM7XX_GPIO_EVEN]));
}
static void npcm7xx_gpio_update_pins(NPCM7xxGPIOState *s, uint32_t diff)
{
uint32_t drive_en;
uint32_t drive_lvl;
uint32_t not_driven;
uint32_t undefined;
uint32_t pin_diff;
uint32_t din_old;
/* Calculate level of each pin driven by GPIO controller. */
drive_lvl = s->regs[NPCM7XX_GPIO_DOUT] ^ s->regs[NPCM7XX_GPIO_POL];
/* If OTYP=1, only drive low (open drain) */
drive_en = s->regs[NPCM7XX_GPIO_OE] & ~(s->regs[NPCM7XX_GPIO_OTYP]
& drive_lvl);
/*
* If a pin is driven to opposite levels by the GPIO controller and the
* external driver, the result is undefined.
*/
undefined = drive_en & s->ext_driven & (drive_lvl ^ s->ext_level);
if (undefined) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: pins have multiple drivers: 0x%" PRIx32 "\n",
DEVICE(s)->canonical_path, undefined);
}
not_driven = ~(drive_en | s->ext_driven);
pin_diff = s->pin_level;
/* Set pins to externally driven level. */
s->pin_level = s->ext_level & s->ext_driven;
/* Set internally driven pins, ignoring any conflicts. */
s->pin_level |= drive_lvl & drive_en;
/* Pull up undriven pins with internal pull-up enabled. */
s->pin_level |= not_driven & s->regs[NPCM7XX_GPIO_PU];
/* Pins not driven, pulled up or pulled down are undefined */
undefined |= not_driven & ~(s->regs[NPCM7XX_GPIO_PU]
| s->regs[NPCM7XX_GPIO_PD]);
/* If any pins changed state, update the outgoing GPIOs. */
pin_diff ^= s->pin_level;
pin_diff |= undefined & diff;
if (pin_diff) {
int i;
for (i = 0; i < NPCM7XX_GPIO_NR_PINS; i++) {
uint32_t mask = BIT(i);
if (pin_diff & mask) {
int level = (undefined & mask) ? -1 : !!(s->pin_level & mask);
trace_npcm7xx_gpio_set_output(DEVICE(s)->canonical_path,
i, level);
qemu_set_irq(s->output[i], level);
}
}
}
/* Calculate new value of DIN after masking and polarity setting. */
din_old = s->regs[NPCM7XX_GPIO_DIN];
s->regs[NPCM7XX_GPIO_DIN] = ((s->pin_level & s->regs[NPCM7XX_GPIO_IEM])
^ s->regs[NPCM7XX_GPIO_POL]);
/* See if any new events triggered because of all this. */
npcm7xx_gpio_update_events(s, din_old ^ s->regs[NPCM7XX_GPIO_DIN]);
}
static bool npcm7xx_gpio_is_locked(NPCM7xxGPIOState *s)
{
return s->regs[NPCM7XX_GPIO_TLOCK1] == 1;
}
static uint64_t npcm7xx_gpio_regs_read(void *opaque, hwaddr addr,
unsigned int size)
{
hwaddr reg = addr / sizeof(uint32_t);
NPCM7xxGPIOState *s = opaque;
uint64_t value = 0;
switch (reg) {
case NPCM7XX_GPIO_TLOCK1 ... NPCM7XX_GPIO_EVEN:
case NPCM7XX_GPIO_EVST ... NPCM7XX_GPIO_ODSC:
value = s->regs[reg];
break;
case NPCM7XX_GPIO_EVENS ... NPCM7XX_GPIO_EVENC:
case NPCM7XX_GPIO_DOS ... NPCM7XX_GPIO_TLOCK2:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: read from write-only register 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, addr);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: read from invalid offset 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, addr);
break;
}
trace_npcm7xx_gpio_read(DEVICE(s)->canonical_path, addr, value);
return value;
}
static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
unsigned int size)
{
hwaddr reg = addr / sizeof(uint32_t);
NPCM7xxGPIOState *s = opaque;
uint32_t value = v;
uint32_t diff;
trace_npcm7xx_gpio_write(DEVICE(s)->canonical_path, addr, v);
if (npcm7xx_gpio_is_locked(s)) {
switch (reg) {
case NPCM7XX_GPIO_TLOCK1:
if (s->regs[NPCM7XX_GPIO_TLOCK2] == NPCM7XX_GPIO_LOCK_MAGIC2 &&
value == NPCM7XX_GPIO_LOCK_MAGIC1) {
s->regs[NPCM7XX_GPIO_TLOCK1] = 0;
s->regs[NPCM7XX_GPIO_TLOCK2] = 0;
}
break;
case NPCM7XX_GPIO_TLOCK2:
s->regs[reg] = value;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to locked register @ 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, addr);
break;
}
return;
}
diff = s->regs[reg] ^ value;
switch (reg) {
case NPCM7XX_GPIO_TLOCK1:
case NPCM7XX_GPIO_TLOCK2:
s->regs[NPCM7XX_GPIO_TLOCK1] = 1;
s->regs[NPCM7XX_GPIO_TLOCK2] = 0;
break;
case NPCM7XX_GPIO_DIN:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to read-only register @ 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, addr);
break;
case NPCM7XX_GPIO_POL:
case NPCM7XX_GPIO_DOUT:
case NPCM7XX_GPIO_OE:
case NPCM7XX_GPIO_OTYP:
case NPCM7XX_GPIO_PU:
case NPCM7XX_GPIO_PD:
case NPCM7XX_GPIO_IEM:
s->regs[reg] = value;
npcm7xx_gpio_update_pins(s, diff);
break;
case NPCM7XX_GPIO_DOS:
s->regs[NPCM7XX_GPIO_DOUT] |= value;
npcm7xx_gpio_update_pins(s, value);
break;
case NPCM7XX_GPIO_DOC:
s->regs[NPCM7XX_GPIO_DOUT] &= ~value;
npcm7xx_gpio_update_pins(s, value);
break;
case NPCM7XX_GPIO_OES:
s->regs[NPCM7XX_GPIO_OE] |= value;
npcm7xx_gpio_update_pins(s, value);
break;
case NPCM7XX_GPIO_OEC:
s->regs[NPCM7XX_GPIO_OE] &= ~value;
npcm7xx_gpio_update_pins(s, value);
break;
case NPCM7XX_GPIO_EVTYP:
case NPCM7XX_GPIO_EVBE:
case NPCM7XX_GPIO_EVEN:
s->regs[reg] = value;
npcm7xx_gpio_update_events(s, 0);
break;
case NPCM7XX_GPIO_EVENS:
s->regs[NPCM7XX_GPIO_EVEN] |= value;
npcm7xx_gpio_update_events(s, 0);
break;
case NPCM7XX_GPIO_EVENC:
s->regs[NPCM7XX_GPIO_EVEN] &= ~value;
npcm7xx_gpio_update_events(s, 0);
break;
case NPCM7XX_GPIO_EVST:
s->regs[reg] &= ~value;
npcm7xx_gpio_update_events(s, 0);
break;
case NPCM7XX_GPIO_MP:
case NPCM7XX_GPIO_DBNC:
case NPCM7XX_GPIO_OSRC:
case NPCM7XX_GPIO_ODSC:
/* Nothing to do; just store the value. */
s->regs[reg] = value;
break;
case NPCM7XX_GPIO_OBL0:
case NPCM7XX_GPIO_OBL1:
case NPCM7XX_GPIO_OBL2:
case NPCM7XX_GPIO_OBL3:
s->regs[reg] = value;
qemu_log_mask(LOG_UNIMP, "%s: Blinking is not implemented\n",
__func__);
break;
case NPCM7XX_GPIO_SPLCK:
case NPCM7XX_GPIO_MPLCK:
qemu_log_mask(LOG_UNIMP, "%s: Per-pin lock is not implemented\n",
__func__);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to invalid offset 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, addr);
break;
}
}
static const MemoryRegionOps npcm7xx_gpio_regs_ops = {
.read = npcm7xx_gpio_regs_read,
.write = npcm7xx_gpio_regs_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
.unaligned = false,
},
};
static void npcm7xx_gpio_set_input(void *opaque, int line, int level)
{
NPCM7xxGPIOState *s = opaque;
trace_npcm7xx_gpio_set_input(DEVICE(s)->canonical_path, line, level);
g_assert(line >= 0 && line < NPCM7XX_GPIO_NR_PINS);
s->ext_driven = deposit32(s->ext_driven, line, 1, level >= 0);
s->ext_level = deposit32(s->ext_level, line, 1, level > 0);
npcm7xx_gpio_update_pins(s, BIT(line));
}
static void npcm7xx_gpio_enter_reset(Object *obj, ResetType type)
{
NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
memset(s->regs, 0, sizeof(s->regs));
s->regs[NPCM7XX_GPIO_PU] = s->reset_pu;
s->regs[NPCM7XX_GPIO_PD] = s->reset_pd;
s->regs[NPCM7XX_GPIO_OSRC] = s->reset_osrc;
s->regs[NPCM7XX_GPIO_ODSC] = s->reset_odsc;
}
static void npcm7xx_gpio_hold_reset(Object *obj)
{
NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
npcm7xx_gpio_update_pins(s, -1);
}
static void npcm7xx_gpio_init(Object *obj)
{
NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
DeviceState *dev = DEVICE(obj);
memory_region_init_io(&s->mmio, obj, &npcm7xx_gpio_regs_ops, s,
"regs", NPCM7XX_GPIO_REGS_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
qdev_init_gpio_in(dev, npcm7xx_gpio_set_input, NPCM7XX_GPIO_NR_PINS);
qdev_init_gpio_out(dev, s->output, NPCM7XX_GPIO_NR_PINS);
}
static const VMStateDescription vmstate_npcm7xx_gpio = {
.name = "npcm7xx-gpio",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT32(pin_level, NPCM7xxGPIOState),
VMSTATE_UINT32(ext_level, NPCM7xxGPIOState),
VMSTATE_UINT32(ext_driven, NPCM7xxGPIOState),
VMSTATE_UINT32_ARRAY(regs, NPCM7xxGPIOState, NPCM7XX_GPIO_NR_REGS),
VMSTATE_END_OF_LIST(),
},
};
static Property npcm7xx_gpio_properties[] = {
/* Bit n set => pin n has pullup enabled by default. */
DEFINE_PROP_UINT32("reset-pullup", NPCM7xxGPIOState, reset_pu, 0),
/* Bit n set => pin n has pulldown enabled by default. */
DEFINE_PROP_UINT32("reset-pulldown", NPCM7xxGPIOState, reset_pd, 0),
/* Bit n set => pin n has high slew rate by default. */
DEFINE_PROP_UINT32("reset-osrc", NPCM7xxGPIOState, reset_osrc, 0),
/* Bit n set => pin n has high drive strength by default. */
DEFINE_PROP_UINT32("reset-odsc", NPCM7xxGPIOState, reset_odsc, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void npcm7xx_gpio_class_init(ObjectClass *klass, void *data)
{
ResettableClass *reset = RESETTABLE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
QEMU_BUILD_BUG_ON(NPCM7XX_GPIO_REGS_END > NPCM7XX_GPIO_NR_REGS);
dc->desc = "NPCM7xx GPIO Controller";
dc->vmsd = &vmstate_npcm7xx_gpio;
reset->phases.enter = npcm7xx_gpio_enter_reset;
reset->phases.hold = npcm7xx_gpio_hold_reset;
device_class_set_props(dc, npcm7xx_gpio_properties);
}
static const TypeInfo npcm7xx_gpio_types[] = {
{
.name = TYPE_NPCM7XX_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCM7xxGPIOState),
.class_init = npcm7xx_gpio_class_init,
.instance_init = npcm7xx_gpio_init,
},
};
DEFINE_TYPES(npcm7xx_gpio_types);

7
hw/gpio/trace-events
View File

@ -1,5 +1,12 @@
# See docs/devel/tracing.txt for syntax documentation.
# npcm7xx_gpio.c
npcm7xx_gpio_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
npcm7xx_gpio_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
npcm7xx_gpio_set_input(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32
npcm7xx_gpio_set_output(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32
npcm7xx_gpio_update_events(const char *id, uint32_t evst, uint32_t even) "%s evst: 0x%08" PRIx32 " even: 0x%08" PRIx32
# nrf51_gpio.c
nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64

808
hw/misc/bcm2835_cprman.c Normal file
View File

@ -0,0 +1,808 @@
/*
* BCM2835 CPRMAN clock manager
*
* Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
/*
* This peripheral is roughly divided into 3 main parts:
* - the PLLs
* - the PLL channels
* - the clock muxes
*
* A main oscillator (xosc) feeds all the PLLs. Each PLLs has one or more
* channels. Those channel are then connected to the clock muxes. Each mux has
* multiples sources (usually the xosc, some of the PLL channels and some "test
* debug" clocks). A mux is configured to select a given source through its
* control register. Each mux has one output clock that also goes out of the
* CPRMAN. This output clock usually connects to another peripheral in the SoC
* (so a given mux is dedicated to a peripheral).
*
* At each level (PLL, channel and mux), the clock can be altered through
* dividers (and multipliers in case of the PLLs), and can be disabled (in this
* case, the next levels see no clock).
*
* This can be sum-up as follows (this is an example and not the actual BCM2835
* clock tree):
*
* /-->[PLL]-|->[PLL channel]--... [mux]--> to peripherals
* | |->[PLL channel] muxes takes [mux]
* | \->[PLL channel] inputs from [mux]
* | some channels [mux]
* [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux]
* | \->[PLL channel] ...-->[mux]
* | [mux]
* \-->[PLL]--->[PLL channel] [mux]
*
* The page at https://elinux.org/The_Undocumented_Pi gives the actual clock
* tree configuration.
*
* The CPRMAN exposes clock outputs with the name of the clock mux suffixed
* with "-out" (e.g. "uart-out", "h264-out", ...).
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "migration/vmstate.h"
#include "hw/qdev-properties.h"
#include "hw/misc/bcm2835_cprman.h"
#include "hw/misc/bcm2835_cprman_internals.h"
#include "trace.h"
/* PLL */
static void pll_reset(DeviceState *dev)
{
CprmanPllState *s = CPRMAN_PLL(dev);
const PLLResetInfo *info = &PLL_RESET_INFO[s->id];
*s->reg_cm = info->cm;
*s->reg_a2w_ctrl = info->a2w_ctrl;
memcpy(s->reg_a2w_ana, info->a2w_ana, sizeof(info->a2w_ana));
*s->reg_a2w_frac = info->a2w_frac;
}
static bool pll_is_locked(const CprmanPllState *pll)
{
return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN)
&& !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST);
}
static void pll_update(CprmanPllState *pll)
{
uint64_t freq, ndiv, fdiv, pdiv;
if (!pll_is_locked(pll)) {
clock_update(pll->out, 0);
return;
}
pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV);
if (!pdiv) {
clock_update(pll->out, 0);
return;
}
ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV);
fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC);
if (pll->reg_a2w_ana[1] & pll->prediv_mask) {
/* The prescaler doubles the parent frequency */
ndiv *= 2;
fdiv *= 2;
}
/*
* We have a multiplier with an integer part (ndiv) and a fractional part
* (fdiv), and a divider (pdiv).
*/
freq = clock_get_hz(pll->xosc_in) *
((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv);
freq /= pdiv;
freq >>= R_A2W_PLLx_FRAC_FRAC_LENGTH;
clock_update_hz(pll->out, freq);
}
static void pll_xosc_update(void *opaque)
{
pll_update(CPRMAN_PLL(opaque));
}
static void pll_init(Object *obj)
{
CprmanPllState *s = CPRMAN_PLL(obj);
s->xosc_in = qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_update, s);
s->out = qdev_init_clock_out(DEVICE(s), "out");
}
static const VMStateDescription pll_vmstate = {
.name = TYPE_CPRMAN_PLL,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_CLOCK(xosc_in, CprmanPllState),
VMSTATE_END_OF_LIST()
}
};
static void pll_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = pll_reset;
dc->vmsd = &pll_vmstate;
}
static const TypeInfo cprman_pll_info = {
.name = TYPE_CPRMAN_PLL,
.parent = TYPE_DEVICE,
.instance_size = sizeof(CprmanPllState),
.class_init = pll_class_init,
.instance_init = pll_init,
};
/* PLL channel */
static void pll_channel_reset(DeviceState *dev)
{
CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(dev);
const PLLChannelResetInfo *info = &PLL_CHANNEL_RESET_INFO[s->id];
*s->reg_a2w_ctrl = info->a2w_ctrl;
}
static bool pll_channel_is_enabled(CprmanPllChannelState *channel)
{
/*
* XXX I'm not sure of the purpose of the LOAD field. The Linux driver does
* not set it when enabling the channel, but does clear it when disabling
* it.
*/
return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE)
&& !(*channel->reg_cm & channel->hold_mask);
}
static void pll_channel_update(CprmanPllChannelState *channel)
{
uint64_t freq, div;
if (!pll_channel_is_enabled(channel)) {
clock_update(channel->out, 0);
return;
}
div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV);
if (!div) {
/*
* It seems that when the divider value is 0, it is considered as
* being maximum by the hardware (see the Linux driver).
*/
div = R_A2W_PLLx_CHANNELy_DIV_MASK;
}
/* Some channels have an additional fixed divider */
freq = clock_get_hz(channel->pll_in) / (div * channel->fixed_divider);
clock_update_hz(channel->out, freq);
}
/* Update a PLL and all its channels */
static void pll_update_all_channels(BCM2835CprmanState *s,
CprmanPllState *pll)
{
size_t i;
pll_update(pll);
for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
CprmanPllChannelState *channel = &s->channels[i];
if (channel->parent == pll->id) {
pll_channel_update(channel);
}
}
}
static void pll_channel_pll_in_update(void *opaque)
{
pll_channel_update(CPRMAN_PLL_CHANNEL(opaque));
}
static void pll_channel_init(Object *obj)
{
CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(obj);
s->pll_in = qdev_init_clock_in(DEVICE(s), "pll-in",
pll_channel_pll_in_update, s);
s->out = qdev_init_clock_out(DEVICE(s), "out");
}
static const VMStateDescription pll_channel_vmstate = {
.name = TYPE_CPRMAN_PLL_CHANNEL,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_CLOCK(pll_in, CprmanPllChannelState),
VMSTATE_END_OF_LIST()
}
};
static void pll_channel_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = pll_channel_reset;
dc->vmsd = &pll_channel_vmstate;
}
static const TypeInfo cprman_pll_channel_info = {
.name = TYPE_CPRMAN_PLL_CHANNEL,
.parent = TYPE_DEVICE,
.instance_size = sizeof(CprmanPllChannelState),
.class_init = pll_channel_class_init,
.instance_init = pll_channel_init,
};
/* clock mux */
static bool clock_mux_is_enabled(CprmanClockMuxState *mux)
{
return FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, ENABLE);
}
static void clock_mux_update(CprmanClockMuxState *mux)
{
uint64_t freq;
uint32_t div, src = FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, SRC);
bool enabled = clock_mux_is_enabled(mux);
*mux->reg_ctl = FIELD_DP32(*mux->reg_ctl, CM_CLOCKx_CTL, BUSY, enabled);
if (!enabled) {
clock_update(mux->out, 0);
return;
}
freq = clock_get_hz(mux->srcs[src]);
if (mux->int_bits == 0 && mux->frac_bits == 0) {
clock_update_hz(mux->out, freq);
return;
}
/*
* The divider has an integer and a fractional part. The size of each part
* varies with the muxes (int_bits and frac_bits). Both parts are
* concatenated, with the integer part always starting at bit 12.
*
* 31 12 11 0
* ------------------------------
* CM_DIV | | int | frac | |
* ------------------------------
* <-----> <------>
* int_bits frac_bits
*/
div = extract32(*mux->reg_div,
R_CM_CLOCKx_DIV_FRAC_LENGTH - mux->frac_bits,
mux->int_bits + mux->frac_bits);
if (!div) {
clock_update(mux->out, 0);
return;
}
freq = muldiv64(freq, 1 << mux->frac_bits, div);
clock_update_hz(mux->out, freq);
}
static void clock_mux_src_update(void *opaque)
{
CprmanClockMuxState **backref = opaque;
CprmanClockMuxState *s = *backref;
CprmanClockMuxSource src = backref - s->backref;
if (FIELD_EX32(*s->reg_ctl, CM_CLOCKx_CTL, SRC) != src) {
return;
}
clock_mux_update(s);
}
static void clock_mux_reset(DeviceState *dev)
{
CprmanClockMuxState *clock = CPRMAN_CLOCK_MUX(dev);
const ClockMuxResetInfo *info = &CLOCK_MUX_RESET_INFO[clock->id];
*clock->reg_ctl = info->cm_ctl;
*clock->reg_div = info->cm_div;
}
static void clock_mux_init(Object *obj)
{
CprmanClockMuxState *s = CPRMAN_CLOCK_MUX(obj);
size_t i;
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) {
char *name = g_strdup_printf("srcs[%zu]", i);
s->backref[i] = s;
s->srcs[i] = qdev_init_clock_in(DEVICE(s), name,
clock_mux_src_update,
&s->backref[i]);
g_free(name);
}
s->out = qdev_init_clock_out(DEVICE(s), "out");
}
static const VMStateDescription clock_mux_vmstate = {
.name = TYPE_CPRMAN_CLOCK_MUX,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_ARRAY_CLOCK(srcs, CprmanClockMuxState,
CPRMAN_NUM_CLOCK_MUX_SRC),
VMSTATE_END_OF_LIST()
}
};
static void clock_mux_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = clock_mux_reset;
dc->vmsd = &clock_mux_vmstate;
}
static const TypeInfo cprman_clock_mux_info = {
.name = TYPE_CPRMAN_CLOCK_MUX,
.parent = TYPE_DEVICE,
.instance_size = sizeof(CprmanClockMuxState),
.class_init = clock_mux_class_init,
.instance_init = clock_mux_init,
};
/* DSI0HSCK mux */
static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState *s)
{
bool src_is_plld = FIELD_EX32(*s->reg_cm, CM_DSI0HSCK, SELPLLD);
Clock *src = src_is_plld ? s->plld_in : s->plla_in;
clock_update(s->out, clock_get(src));
}
static void dsi0hsck_mux_in_update(void *opaque)
{
dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque));
}
static void dsi0hsck_mux_init(Object *obj)
{
CprmanDsi0HsckMuxState *s = CPRMAN_DSI0HSCK_MUX(obj);
DeviceState *dev = DEVICE(obj);
s->plla_in = qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_update, s);
s->plld_in = qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_update, s);
s->out = qdev_init_clock_out(DEVICE(s), "out");
}
static const VMStateDescription dsi0hsck_mux_vmstate = {
.name = TYPE_CPRMAN_DSI0HSCK_MUX,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_CLOCK(plla_in, CprmanDsi0HsckMuxState),
VMSTATE_CLOCK(plld_in, CprmanDsi0HsckMuxState),
VMSTATE_END_OF_LIST()
}
};
static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &dsi0hsck_mux_vmstate;
}
static const TypeInfo cprman_dsi0hsck_mux_info = {
.name = TYPE_CPRMAN_DSI0HSCK_MUX,
.parent = TYPE_DEVICE,
.instance_size = sizeof(CprmanDsi0HsckMuxState),
.class_init = dsi0hsck_mux_class_init,
.instance_init = dsi0hsck_mux_init,
};
/* CPRMAN "top level" model */
static uint32_t get_cm_lock(const BCM2835CprmanState *s)
{
static const int CM_LOCK_MAPPING[CPRMAN_NUM_PLL] = {
[CPRMAN_PLLA] = R_CM_LOCK_FLOCKA_SHIFT,
[CPRMAN_PLLC] = R_CM_LOCK_FLOCKC_SHIFT,
[CPRMAN_PLLD] = R_CM_LOCK_FLOCKD_SHIFT,
[CPRMAN_PLLH] = R_CM_LOCK_FLOCKH_SHIFT,
[CPRMAN_PLLB] = R_CM_LOCK_FLOCKB_SHIFT,
};
uint32_t r = 0;
size_t i;
for (i = 0; i < CPRMAN_NUM_PLL; i++) {
r |= pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i];
}
return r;
}
static uint64_t cprman_read(void *opaque, hwaddr offset,
unsigned size)
{
BCM2835CprmanState *s = CPRMAN(opaque);
uint64_t r = 0;
size_t idx = offset / sizeof(uint32_t);
switch (idx) {
case R_CM_LOCK:
r = get_cm_lock(s);
break;
default:
r = s->regs[idx];
}
trace_bcm2835_cprman_read(offset, r);
return r;
}
static inline void update_pll_and_channels_from_cm(BCM2835CprmanState *s,
size_t idx)
{
size_t i;
for (i = 0; i < CPRMAN_NUM_PLL; i++) {
if (PLL_INIT_INFO[i].cm_offset == idx) {
pll_update_all_channels(s, &s->plls[i]);
return;
}
}
}
static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t idx)
{
size_t i;
for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
if (PLL_CHANNEL_INIT_INFO[i].a2w_ctrl_offset == idx) {
pll_channel_update(&s->channels[i]);
return;
}
}
}
static inline void update_mux_from_cm(BCM2835CprmanState *s, size_t idx)
{
size_t i;
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
if ((CLOCK_MUX_INIT_INFO[i].cm_offset == idx) ||
(CLOCK_MUX_INIT_INFO[i].cm_offset + 4 == idx)) {
/* matches CM_CTL or CM_DIV mux register */
clock_mux_update(&s->clock_muxes[i]);
return;
}
}
}
#define CASE_PLL_A2W_REGS(pll_) \
case R_A2W_ ## pll_ ## _CTRL: \
case R_A2W_ ## pll_ ## _ANA0: \
case R_A2W_ ## pll_ ## _ANA1: \
case R_A2W_ ## pll_ ## _ANA2: \
case R_A2W_ ## pll_ ## _ANA3: \
case R_A2W_ ## pll_ ## _FRAC
static void cprman_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
BCM2835CprmanState *s = CPRMAN(opaque);
size_t idx = offset / sizeof(uint32_t);
if (FIELD_EX32(value, CPRMAN, PASSWORD) != CPRMAN_PASSWORD) {
trace_bcm2835_cprman_write_invalid_magic(offset, value);
return;
}
value &= ~R_CPRMAN_PASSWORD_MASK;
trace_bcm2835_cprman_write(offset, value);
s->regs[idx] = value;
switch (idx) {
case R_CM_PLLA ... R_CM_PLLH:
case R_CM_PLLB:
/*
* A given CM_PLLx register is shared by both the PLL and the channels
* of this PLL.
*/
update_pll_and_channels_from_cm(s, idx);
break;
CASE_PLL_A2W_REGS(PLLA) :
pll_update(&s->plls[CPRMAN_PLLA]);
break;
CASE_PLL_A2W_REGS(PLLC) :
pll_update(&s->plls[CPRMAN_PLLC]);
break;
CASE_PLL_A2W_REGS(PLLD) :
pll_update(&s->plls[CPRMAN_PLLD]);
break;
CASE_PLL_A2W_REGS(PLLH) :
pll_update(&s->plls[CPRMAN_PLLH]);
break;
CASE_PLL_A2W_REGS(PLLB) :
pll_update(&s->plls[CPRMAN_PLLB]);
break;
case R_A2W_PLLA_DSI0:
case R_A2W_PLLA_CORE:
case R_A2W_PLLA_PER:
case R_A2W_PLLA_CCP2:
case R_A2W_PLLC_CORE2:
case R_A2W_PLLC_CORE1:
case R_A2W_PLLC_PER:
case R_A2W_PLLC_CORE0:
case R_A2W_PLLD_DSI0:
case R_A2W_PLLD_CORE:
case R_A2W_PLLD_PER:
case R_A2W_PLLD_DSI1:
case R_A2W_PLLH_AUX:
case R_A2W_PLLH_RCAL:
case R_A2W_PLLH_PIX:
case R_A2W_PLLB_ARM:
update_channel_from_a2w(s, idx);
break;
case R_CM_GNRICCTL ... R_CM_SMIDIV:
case R_CM_TCNTCNT ... R_CM_VECDIV:
case R_CM_PULSECTL ... R_CM_PULSEDIV:
case R_CM_SDCCTL ... R_CM_ARMCTL:
case R_CM_AVEOCTL ... R_CM_EMMCDIV:
case R_CM_EMMC2CTL ... R_CM_EMMC2DIV:
update_mux_from_cm(s, idx);
break;
case R_CM_DSI0HSCK:
dsi0hsck_mux_update(&s->dsi0hsck_mux);
break;
}
}
#undef CASE_PLL_A2W_REGS
static const MemoryRegionOps cprman_ops = {
.read = cprman_read,
.write = cprman_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
/*
* Although this hasn't been checked against real hardware, nor the
* information can be found in a datasheet, it seems reasonable because
* of the "PASSWORD" magic value found in every registers.
*/
.min_access_size = 4,
.max_access_size = 4,
.unaligned = false,
},
.impl = {
.max_access_size = 4,
},
};
static void cprman_reset(DeviceState *dev)
{
BCM2835CprmanState *s = CPRMAN(dev);
size_t i;
memset(s->regs, 0, sizeof(s->regs));
for (i = 0; i < CPRMAN_NUM_PLL; i++) {
device_cold_reset(DEVICE(&s->plls[i]));
}
for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
device_cold_reset(DEVICE(&s->channels[i]));
}
device_cold_reset(DEVICE(&s->dsi0hsck_mux));
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
device_cold_reset(DEVICE(&s->clock_muxes[i]));
}
clock_update_hz(s->xosc, s->xosc_freq);
}
static void cprman_init(Object *obj)
{
BCM2835CprmanState *s = CPRMAN(obj);
size_t i;
for (i = 0; i < CPRMAN_NUM_PLL; i++) {
object_initialize_child(obj, PLL_INIT_INFO[i].name,
&s->plls[i], TYPE_CPRMAN_PLL);
set_pll_init_info(s, &s->plls[i], i);
}
for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
object_initialize_child(obj, PLL_CHANNEL_INIT_INFO[i].name,
&s->channels[i],
TYPE_CPRMAN_PLL_CHANNEL);
set_pll_channel_init_info(s, &s->channels[i], i);
}
object_initialize_child(obj, "dsi0hsck-mux",
&s->dsi0hsck_mux, TYPE_CPRMAN_DSI0HSCK_MUX);
s->dsi0hsck_mux.reg_cm = &s->regs[R_CM_DSI0HSCK];
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
char *alias;
object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name,
&s->clock_muxes[i],
TYPE_CPRMAN_CLOCK_MUX);
set_clock_mux_init_info(s, &s->clock_muxes[i], i);
/* Expose muxes output as CPRMAN outputs */
alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name);
qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias);
g_free(alias);
}
s->xosc = clock_new(obj, "xosc");
s->gnd = clock_new(obj, "gnd");
clock_set(s->gnd, 0);
memory_region_init_io(&s->iomem, obj, &cprman_ops,
s, "bcm2835-cprman", 0x2000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
}
static void connect_mux_sources(BCM2835CprmanState *s,
CprmanClockMuxState *mux,
const CprmanPllChannel *clk_mapping)
{
size_t i;
Clock *td0 = s->clock_muxes[CPRMAN_CLOCK_TD0].out;
Clock *td1 = s->clock_muxes[CPRMAN_CLOCK_TD1].out;
/* For sources from 0 to 3. Source 4 to 9 are mux specific */
Clock * const CLK_SRC_MAPPING[] = {
[CPRMAN_CLOCK_SRC_GND] = s->gnd,
[CPRMAN_CLOCK_SRC_XOSC] = s->xosc,
[CPRMAN_CLOCK_SRC_TD0] = td0,
[CPRMAN_CLOCK_SRC_TD1] = td1,
};
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) {
CprmanPllChannel mapping = clk_mapping[i];
Clock *src;
if (mapping == CPRMAN_CLOCK_SRC_FORCE_GROUND) {
src = s->gnd;
} else if (mapping == CPRMAN_CLOCK_SRC_DSI0HSCK) {
src = s->dsi0hsck_mux.out;
} else if (i < CPRMAN_CLOCK_SRC_PLLA) {
src = CLK_SRC_MAPPING[i];
} else {
src = s->channels[mapping].out;
}
clock_set_source(mux->srcs[i], src);
}
}
static void cprman_realize(DeviceState *dev, Error **errp)
{
BCM2835CprmanState *s = CPRMAN(dev);
size_t i;
for (i = 0; i < CPRMAN_NUM_PLL; i++) {
CprmanPllState *pll = &s->plls[i];
clock_set_source(pll->xosc_in, s->xosc);
if (!qdev_realize(DEVICE(pll), NULL, errp)) {
return;
}
}
for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
CprmanPllChannelState *channel = &s->channels[i];
CprmanPll parent = PLL_CHANNEL_INIT_INFO[i].parent;
Clock *parent_clk = s->plls[parent].out;
clock_set_source(channel->pll_in, parent_clk);
if (!qdev_realize(DEVICE(channel), NULL, errp)) {
return;
}
}
clock_set_source(s->dsi0hsck_mux.plla_in,
s->channels[CPRMAN_PLLA_CHANNEL_DSI0].out);
clock_set_source(s->dsi0hsck_mux.plld_in,
s->channels[CPRMAN_PLLD_CHANNEL_DSI0].out);
if (!qdev_realize(DEVICE(&s->dsi0hsck_mux), NULL, errp)) {
return;
}
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
CprmanClockMuxState *clock_mux = &s->clock_muxes[i];
connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mapping);
if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) {
return;
}
}
}
static const VMStateDescription cprman_vmstate = {
.name = TYPE_BCM2835_CPRMAN,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, BCM2835CprmanState, CPRMAN_NUM_REGS),
VMSTATE_END_OF_LIST()
}
};
static Property cprman_properties[] = {
DEFINE_PROP_UINT32("xosc-freq-hz", BCM2835CprmanState, xosc_freq, 19200000),
DEFINE_PROP_END_OF_LIST()
};
static void cprman_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = cprman_realize;
dc->reset = cprman_reset;
dc->vmsd = &cprman_vmstate;
device_class_set_props(dc, cprman_properties);
}
static const TypeInfo cprman_info = {
.name = TYPE_BCM2835_CPRMAN,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835CprmanState),
.class_init = cprman_class_init,
.instance_init = cprman_init,
};
static void cprman_register_types(void)
{
type_register_static(&cprman_info);
type_register_static(&cprman_pll_info);
type_register_static(&cprman_pll_channel_info);
type_register_static(&cprman_clock_mux_info);
type_register_static(&cprman_dsi0hsck_mux_info);
}
type_init(cprman_register_types);

2
hw/misc/meson.build
View File

@ -60,6 +60,7 @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
'npcm7xx_clk.c',
'npcm7xx_gcr.c',
'npcm7xx_rng.c',
))
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
'omap_clk.c',
@ -74,6 +75,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
'bcm2835_property.c',
'bcm2835_rng.c',
'bcm2835_thermal.c',
'bcm2835_cprman.c',
))
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))

28
hw/misc/npcm7xx_clk.c
View File

@ -17,6 +17,7 @@
#include "qemu/osdep.h"
#include "hw/misc/npcm7xx_clk.h"
#include "hw/timer/npcm7xx_timer.h"
#include "migration/vmstate.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
@ -24,6 +25,7 @@
#include "qemu/timer.h"
#include "qemu/units.h"
#include "trace.h"
#include "sysemu/watchdog.h"
#define PLLCON_LOKI BIT(31)
#define PLLCON_LOKS BIT(30)
@ -87,6 +89,12 @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
};
/* Register Field Definitions */
#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
/* The number of watchdogs that can trigger a reset. */
#define NPCM7XX_NR_WATCHDOGS (3)
static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
@ -187,6 +195,24 @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
s->regs[reg] = value;
}
/* Perform reset action triggered by a watchdog */
static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
int level)
{
NPCM7xxCLKState *clk = NPCM7XX_CLK(opaque);
uint32_t rcr;
g_assert(n >= 0 && n <= NPCM7XX_NR_WATCHDOGS);
rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n];
if (rcr & NPCM7XX_CLK_WDRCR_CA9C) {
watchdog_perform_action();
} else {
qemu_log_mask(LOG_UNIMP,
"%s: only CPU reset is implemented. (requested 0x%" PRIx32")\n",
__func__, rcr);
}
}
static const struct MemoryRegionOps npcm7xx_clk_ops = {
.read = npcm7xx_clk_read,
.write = npcm7xx_clk_write,
@ -226,6 +252,8 @@ static void npcm7xx_clk_init(Object *obj)
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
TYPE_NPCM7XX_CLK, 4 * KiB);
sysbus_init_mmio(&s->parent, &s->iomem);
qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
}
static const VMStateDescription vmstate_npcm7xx_clk = {

180
hw/misc/npcm7xx_rng.c Normal file
View File

@ -0,0 +1,180 @@
/*
* Nuvoton NPCM7xx Random Number Generator.
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include "qemu/osdep.h"
#include "hw/misc/npcm7xx_rng.h"
#include "migration/vmstate.h"
#include "qemu/bitops.h"
#include "qemu/guest-random.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/units.h"
#include "trace.h"
#define NPCM7XX_RNG_REGS_SIZE (4 * KiB)
#define NPCM7XX_RNGCS (0x00)
#define NPCM7XX_RNGCS_CLKP(rv) extract32(rv, 2, 4)
#define NPCM7XX_RNGCS_DVALID BIT(1)
#define NPCM7XX_RNGCS_RNGE BIT(0)
#define NPCM7XX_RNGD (0x04)
#define NPCM7XX_RNGMODE (0x08)
#define NPCM7XX_RNGMODE_NORMAL (0x02)
static bool npcm7xx_rng_is_enabled(NPCM7xxRNGState *s)
{
return (s->rngcs & NPCM7XX_RNGCS_RNGE) &&
(s->rngmode == NPCM7XX_RNGMODE_NORMAL);
}
static uint64_t npcm7xx_rng_read(void *opaque, hwaddr offset, unsigned size)
{
NPCM7xxRNGState *s = opaque;
uint64_t value = 0;
switch (offset) {
case NPCM7XX_RNGCS:
/*
* If the RNG is enabled, but we don't have any valid random data, try
* obtaining some and update the DVALID bit accordingly.
*/
if (!npcm7xx_rng_is_enabled(s)) {
s->rngcs &= ~NPCM7XX_RNGCS_DVALID;
} else if (!(s->rngcs & NPCM7XX_RNGCS_DVALID)) {
uint8_t byte = 0;
if (qemu_guest_getrandom(&byte, sizeof(byte), NULL) == 0) {
s->rngd = byte;
s->rngcs |= NPCM7XX_RNGCS_DVALID;
}
}
value = s->rngcs;
break;
case NPCM7XX_RNGD:
if (npcm7xx_rng_is_enabled(s) && s->rngcs & NPCM7XX_RNGCS_DVALID) {
s->rngcs &= ~NPCM7XX_RNGCS_DVALID;
value = s->rngd;
s->rngd = 0;
}
break;
case NPCM7XX_RNGMODE:
value = s->rngmode;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: read from invalid offset 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, offset);
break;
}
trace_npcm7xx_rng_read(offset, value, size);
return value;
}
static void npcm7xx_rng_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
NPCM7xxRNGState *s = opaque;
trace_npcm7xx_rng_write(offset, value, size);
switch (offset) {
case NPCM7XX_RNGCS:
s->rngcs &= NPCM7XX_RNGCS_DVALID;
s->rngcs |= value & ~NPCM7XX_RNGCS_DVALID;
break;
case NPCM7XX_RNGD:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to read-only register @ 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, offset);
break;
case NPCM7XX_RNGMODE:
s->rngmode = value;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to invalid offset 0x%" HWADDR_PRIx "\n",
DEVICE(s)->canonical_path, offset);
break;
}
}
static const MemoryRegionOps npcm7xx_rng_ops = {
.read = npcm7xx_rng_read,
.write = npcm7xx_rng_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 4,
.unaligned = false,
},
};
static void npcm7xx_rng_enter_reset(Object *obj, ResetType type)
{
NPCM7xxRNGState *s = NPCM7XX_RNG(obj);
s->rngcs = 0;
s->rngd = 0;
s->rngmode = 0;
}
static void npcm7xx_rng_init(Object *obj)
{
NPCM7xxRNGState *s = NPCM7XX_RNG(obj);
memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
NPCM7XX_RNG_REGS_SIZE);
sysbus_init_mmio(&s->parent, &s->iomem);
}
static const VMStateDescription vmstate_npcm7xx_rng = {
.name = "npcm7xx-rng",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT8(rngcs, NPCM7xxRNGState),
VMSTATE_UINT8(rngd, NPCM7xxRNGState),
VMSTATE_UINT8(rngmode, NPCM7xxRNGState),
VMSTATE_END_OF_LIST(),
},
};
static void npcm7xx_rng_class_init(ObjectClass *klass, void *data)
{
ResettableClass *rc = RESETTABLE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "NPCM7xx Random Number Generator";
dc->vmsd = &vmstate_npcm7xx_rng;
rc->phases.enter = npcm7xx_rng_enter_reset;
}
static const TypeInfo npcm7xx_rng_types[] = {
{
.name = TYPE_NPCM7XX_RNG,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCM7xxRNGState),
.class_init = npcm7xx_rng_class_init,
.instance_init = npcm7xx_rng_init,
},
};
DEFINE_TYPES(npcm7xx_rng_types);

9
hw/misc/trace-events
View File

@ -116,6 +116,10 @@ npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
# npcm7xx_rng.c
npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
# stm32f4xx_syscfg.c
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
@ -228,3 +232,8 @@ led_change_intensity(const char *color, const char *desc, uint8_t old_intensity_
# pca9552.c
pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]"
pca955x_gpio_change(const char *description, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u"
# bcm2835_cprman.c
bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64

124
hw/timer/armv7m_systick.c
View File

@ -39,26 +39,6 @@ static inline int64_t systick_scale(SysTickState *s)
}
}
static void systick_reload(SysTickState *s, int reset)
{
/* The Cortex-M3 Devices Generic User Guide says that "When the
* ENABLE bit is set to 1, the counter loads the RELOAD value from the
* SYST RVR register and then counts down". So, we need to check the
* ENABLE bit before reloading the value.
*/
trace_systick_reload();
if ((s->control & SYSTICK_ENABLE) == 0) {
return;
}
if (reset) {
s->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
s->tick += (s->reload + 1) * systick_scale(s);
timer_mod(s->timer, s->tick);
}
static void systick_timer_tick(void *opaque)
{
SysTickState *s = (SysTickState *)opaque;
@ -70,10 +50,12 @@ static void systick_timer_tick(void *opaque)
/* Tell the NVIC to pend the SysTick exception */
qemu_irq_pulse(s->irq);
}
if (s->reload == 0) {
s->control &= ~SYSTICK_ENABLE;
} else {
systick_reload(s, 0);
if (ptimer_get_limit(s->ptimer) == 0) {
/*
* Timer expiry with SYST_RVR zero disables the timer
* (but doesn't clear SYST_CSR.ENABLE)
*/
ptimer_stop(s->ptimer);
}
}
@ -94,30 +76,11 @@ static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data,
s->control &= ~SYSTICK_COUNTFLAG;
break;
case 0x4: /* SysTick Reload Value. */
val = s->reload;
val = ptimer_get_limit(s->ptimer);
break;
case 0x8: /* SysTick Current Value. */
{
int64_t t;
if ((s->control & SYSTICK_ENABLE) == 0) {
val = 0;
break;
}
t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (t >= s->tick) {
val = 0;
break;
}
val = ((s->tick - (t + 1)) / systick_scale(s)) + 1;
/* The interrupt in triggered when the timer reaches zero.
However the counter is not reloaded until the next clock
tick. This is a hack to return zero during the first tick. */
if (val > s->reload) {
val = 0;
}
val = ptimer_get_count(s->ptimer);
break;
}
case 0xc: /* SysTick Calibration Value. */
val = 10000;
break;
@ -149,39 +112,50 @@ static MemTxResult systick_write(void *opaque, hwaddr addr,
switch (addr) {
case 0x0: /* SysTick Control and Status. */
{
uint32_t oldval = s->control;
uint32_t oldval;
ptimer_transaction_begin(s->ptimer);
oldval = s->control;
s->control &= 0xfffffff8;
s->control |= value & 7;
if ((oldval ^ value) & SYSTICK_ENABLE) {
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (value & SYSTICK_ENABLE) {
if (s->tick) {
s->tick += now;
timer_mod(s->timer, s->tick);
} else {
systick_reload(s, 1);
}
/*
* Always reload the period in case board code has
* changed system_clock_scale. If we ever replace that
* global with a more sensible API then we might be able
* to set the period only when it actually changes.
*/
ptimer_set_period(s->ptimer, systick_scale(s));
ptimer_run(s->ptimer, 0);
} else {
timer_del(s->timer);
s->tick -= now;
if (s->tick < 0) {
s->tick = 0;
}
ptimer_stop(s->ptimer);
}
} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
/* This is a hack. Force the timer to be reloaded
when the reference clock is changed. */
systick_reload(s, 1);
ptimer_set_period(s->ptimer, systick_scale(s));
}
ptimer_transaction_commit(s->ptimer);
break;
}
case 0x4: /* SysTick Reload Value. */
s->reload = value;
ptimer_transaction_begin(s->ptimer);
ptimer_set_limit(s->ptimer, value & 0xffffff, 0);
ptimer_transaction_commit(s->ptimer);
break;
case 0x8: /* SysTick Current Value. Writes reload the timer. */
systick_reload(s, 1);
case 0x8: /* SysTick Current Value. */
/*
* Writing any value clears SYST_CVR to zero and clears
* SYST_CSR.COUNTFLAG. The counter will then reload from SYST_RVR
* on the next clock edge unless SYST_RVR is zero.
*/
ptimer_transaction_begin(s->ptimer);
if (ptimer_get_limit(s->ptimer) == 0) {
ptimer_stop(s->ptimer);
}
ptimer_set_count(s->ptimer, 0);
s->control &= ~SYSTICK_COUNTFLAG;
ptimer_transaction_commit(s->ptimer);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
@ -210,10 +184,13 @@ static void systick_reset(DeviceState *dev)
*/
assert(system_clock_scale != 0);
ptimer_transaction_begin(s->ptimer);
s->control = 0;
s->reload = 0;
s->tick = 0;
timer_del(s->timer);
ptimer_stop(s->ptimer);
ptimer_set_count(s->ptimer, 0);
ptimer_set_limit(s->ptimer, 0, 0);
ptimer_set_period(s->ptimer, systick_scale(s));
ptimer_transaction_commit(s->ptimer);
}
static void systick_instance_init(Object *obj)
@ -229,18 +206,21 @@ static void systick_instance_init(Object *obj)
static void systick_realize(DeviceState *dev, Error **errp)
{
SysTickState *s = SYSTICK(dev);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
s->ptimer = ptimer_init(systick_timer_tick, s,
PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN |
PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
}
static const VMStateDescription vmstate_systick = {
.name = "armv7m_systick",
.version_id = 1,
.minimum_version_id = 1,
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(control, SysTickState),
VMSTATE_UINT32(reload, SysTickState),
VMSTATE_INT64(tick, SysTickState),
VMSTATE_TIMER_PTR(timer, SysTickState),
VMSTATE_PTIMER(ptimer, SysTickState),
VMSTATE_END_OF_LIST()
}
};

270
hw/timer/npcm7xx_timer.c
View File

@ -17,6 +17,7 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/misc/npcm7xx_clk.h"
#include "hw/timer/npcm7xx_timer.h"
#include "migration/vmstate.h"
@ -60,6 +61,50 @@ enum NPCM7xxTimerRegisters {
#define NPCM7XX_TCSR_PRESCALE_START 0
#define NPCM7XX_TCSR_PRESCALE_LEN 8
#define NPCM7XX_WTCR_WTCLK(rv) extract32(rv, 10, 2)
#define NPCM7XX_WTCR_FREEZE_EN BIT(9)
#define NPCM7XX_WTCR_WTE BIT(7)
#define NPCM7XX_WTCR_WTIE BIT(6)
#define NPCM7XX_WTCR_WTIS(rv) extract32(rv, 4, 2)
#define NPCM7XX_WTCR_WTIF BIT(3)
#define NPCM7XX_WTCR_WTRF BIT(2)
#define NPCM7XX_WTCR_WTRE BIT(1)
#define NPCM7XX_WTCR_WTR BIT(0)
/*
* The number of clock cycles between interrupt and reset in watchdog, used
* by the software to handle the interrupt before system is reset.
*/
#define NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES 1024
/* Start or resume the timer. */
static void npcm7xx_timer_start(NPCM7xxBaseTimer *t)
{
int64_t now;
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
t->expires_ns = now + t->remaining_ns;
timer_mod(&t->qtimer, t->expires_ns);
}
/* Stop counting. Record the time remaining so we can continue later. */
static void npcm7xx_timer_pause(NPCM7xxBaseTimer *t)
{
int64_t now;
timer_del(&t->qtimer);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
t->remaining_ns = t->expires_ns - now;
}
/* Delete the timer and reset it to default state. */
static void npcm7xx_timer_clear(NPCM7xxBaseTimer *t)
{
timer_del(&t->qtimer);
t->expires_ns = 0;
t->remaining_ns = 0;
}
/*
* Returns the index of timer in the tc->timer array. This can be used to
* locate the registers that belong to this timer.
@ -102,6 +147,52 @@ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
return count;
}
static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
{
switch (NPCM7XX_WTCR_WTCLK(t->wtcr)) {
case 0:
return 1;
case 1:
return 256;
case 2:
return 2048;
case 3:
return 65536;
default:
g_assert_not_reached();
}
}
static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
int64_t cycles)
{
uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
/*
* The reset function always clears the current timer. The caller of the
* this needs to decide whether to start the watchdog timer based on
* specific flag in WTCR.
*/
npcm7xx_timer_clear(&t->base_timer);
ns *= prescaler;
t->base_timer.remaining_ns = ns;
}
static void npcm7xx_watchdog_timer_reset(NPCM7xxWatchdogTimer *t)
{
int64_t cycles = 1;
uint32_t s = NPCM7XX_WTCR_WTIS(t->wtcr);
g_assert(s <= 3);
cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT;
cycles <<= 2 * s;
npcm7xx_watchdog_timer_reset_cycles(t, cycles);
}
/*
* Raise the interrupt line if there's a pending interrupt and interrupts are
* enabled for this timer. If not, lower it.
@ -116,16 +207,6 @@ static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
}
/* Start or resume the timer. */
static void npcm7xx_timer_start(NPCM7xxTimer *t)
{
int64_t now;
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
t->expires_ns = now + t->remaining_ns;
timer_mod(&t->qtimer, t->expires_ns);
}
/*
* Called when the counter reaches zero. Sets the interrupt flag, and either
* restarts or disables the timer.
@ -138,9 +219,9 @@ static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
tc->tisr |= BIT(index);
if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
if (t->tcsr & NPCM7XX_TCSR_CEN) {
npcm7xx_timer_start(t);
npcm7xx_timer_start(&t->base_timer);
}
} else {
t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
@ -149,18 +230,6 @@ static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
npcm7xx_timer_check_interrupt(t);
}
/* Stop counting. Record the time remaining so we can continue later. */
static void npcm7xx_timer_pause(NPCM7xxTimer *t)
{
int64_t now;
timer_del(&t->qtimer);
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
t->remaining_ns = t->expires_ns - now;
if (t->remaining_ns <= 0) {
npcm7xx_timer_reached_zero(t);
}
}
/*
* Restart the timer from its initial value. If the timer was enabled and stays
@ -170,10 +239,10 @@ static void npcm7xx_timer_pause(NPCM7xxTimer *t)
*/
static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
{
t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
npcm7xx_timer_start(t);
npcm7xx_timer_start(&t->base_timer);
}
}
@ -184,10 +253,10 @@ static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
if (t->tcsr & NPCM7XX_TCSR_CEN) {
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
return npcm7xx_timer_ns_to_count(t, t->expires_ns - now);
return npcm7xx_timer_ns_to_count(t, t->base_timer.expires_ns - now);
}
return npcm7xx_timer_ns_to_count(t, t->remaining_ns);
return npcm7xx_timer_ns_to_count(t, t->base_timer.remaining_ns);
}
static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
@ -219,9 +288,9 @@ static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
/* Recalculate time remaining based on the current TDR value. */
t->remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
npcm7xx_timer_start(t);
npcm7xx_timer_start(&t->base_timer);
}
}
@ -235,10 +304,13 @@ static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
if (new_tcsr & NPCM7XX_TCSR_CEN) {
t->tcsr |= NPCM7XX_TCSR_CACT;
npcm7xx_timer_start(t);
npcm7xx_timer_start(&t->base_timer);
} else {
t->tcsr &= ~NPCM7XX_TCSR_CACT;
npcm7xx_timer_pause(t);
npcm7xx_timer_pause(&t->base_timer);
if (t->base_timer.remaining_ns <= 0) {
npcm7xx_timer_reached_zero(t);
}
}
}
}
@ -259,9 +331,47 @@ static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState *s, uint32_t value)
if (value & (1U << i)) {
npcm7xx_timer_check_interrupt(&s->timer[i]);
}
}
}
static void npcm7xx_timer_write_wtcr(NPCM7xxWatchdogTimer *t, uint32_t new_wtcr)
{
uint32_t old_wtcr = t->wtcr;
/*
* WTIF and WTRF are cleared by writing 1. Writing 0 makes these bits
* unchanged.
*/
if (new_wtcr & NPCM7XX_WTCR_WTIF) {
new_wtcr &= ~NPCM7XX_WTCR_WTIF;
} else if (old_wtcr & NPCM7XX_WTCR_WTIF) {
new_wtcr |= NPCM7XX_WTCR_WTIF;
}
if (new_wtcr & NPCM7XX_WTCR_WTRF) {
new_wtcr &= ~NPCM7XX_WTCR_WTRF;
} else if (old_wtcr & NPCM7XX_WTCR_WTRF) {
new_wtcr |= NPCM7XX_WTCR_WTRF;
}
t->wtcr = new_wtcr;
if (new_wtcr & NPCM7XX_WTCR_WTR) {
t->wtcr &= ~NPCM7XX_WTCR_WTR;
npcm7xx_watchdog_timer_reset(t);
if (new_wtcr & NPCM7XX_WTCR_WTE) {
npcm7xx_timer_start(&t->base_timer);
}
} else if ((old_wtcr ^ new_wtcr) & NPCM7XX_WTCR_WTE) {
if (new_wtcr & NPCM7XX_WTCR_WTE) {
npcm7xx_timer_start(&t->base_timer);
} else {
npcm7xx_timer_pause(&t->base_timer);
}
}
}
static hwaddr npcm7xx_tcsr_index(hwaddr reg)
{
switch (reg) {
@ -353,7 +463,7 @@ static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size)
break;
case NPCM7XX_TIMER_WTCR:
value = s->wtcr;
value = s->watchdog_timer.wtcr;
break;
default:
@ -409,8 +519,7 @@ static void npcm7xx_timer_write(void *opaque, hwaddr offset,
return;
case NPCM7XX_TIMER_WTCR:
qemu_log_mask(LOG_UNIMP, "%s: WTCR write not implemented: 0x%08x\n",
__func__, value);
npcm7xx_timer_write_wtcr(&s->watchdog_timer, value);
return;
}
@ -448,15 +557,42 @@ static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
NPCM7xxTimer *t = &s->timer[i];
timer_del(&t->qtimer);
t->expires_ns = 0;
t->remaining_ns = 0;
npcm7xx_timer_clear(&t->base_timer);
t->tcsr = 0x00000005;
t->ticr = 0x00000000;
}
s->tisr = 0x00000000;
s->wtcr = 0x00000400;
/*
* Set WTCLK to 1(default) and reset all flags except WTRF.
* WTRF is not reset during a core domain reset.
*/
s->watchdog_timer.wtcr = 0x00000400 | (s->watchdog_timer.wtcr &
NPCM7XX_WTCR_WTRF);
}
static void npcm7xx_watchdog_timer_expired(void *opaque)
{
NPCM7xxWatchdogTimer *t = opaque;
if (t->wtcr & NPCM7XX_WTCR_WTE) {
if (t->wtcr & NPCM7XX_WTCR_WTIF) {
if (t->wtcr & NPCM7XX_WTCR_WTRE) {
t->wtcr |= NPCM7XX_WTCR_WTRF;
/* send reset signal to CLK module*/
qemu_irq_raise(t->reset_signal);
}
} else {
t->wtcr |= NPCM7XX_WTCR_WTIF;
if (t->wtcr & NPCM7XX_WTCR_WTIE) {
/* send interrupt */
qemu_irq_raise(t->irq);
}
npcm7xx_watchdog_timer_reset_cycles(t,
NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES);
npcm7xx_timer_start(&t->base_timer);
}
}
}
static void npcm7xx_timer_hold_reset(Object *obj)
@ -467,6 +603,7 @@ static void npcm7xx_timer_hold_reset(Object *obj)
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
qemu_irq_lower(s->timer[i].irq);
}
qemu_irq_lower(s->watchdog_timer.irq);
}
static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
@ -474,43 +611,80 @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
SysBusDevice *sbd = &s->parent;
int i;
NPCM7xxWatchdogTimer *w;
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
NPCM7xxTimer *t = &s->timer[i];
t->ctrl = s;
timer_init_ns(&t->qtimer, QEMU_CLOCK_VIRTUAL, npcm7xx_timer_expired, t);
timer_init_ns(&t->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
npcm7xx_timer_expired, t);
sysbus_init_irq(sbd, &t->irq);
}
w = &s->watchdog_timer;
w->ctrl = s;
timer_init_ns(&w->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
npcm7xx_watchdog_timer_expired, w);
sysbus_init_irq(sbd, &w->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
TYPE_NPCM7XX_TIMER, 4 * KiB);
sysbus_init_mmio(sbd, &s->iomem);
qdev_init_gpio_out_named(dev, &w->reset_signal,
NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
}
static const VMStateDescription vmstate_npcm7xx_timer = {
.name = "npcm7xx-timer",
static const VMStateDescription vmstate_npcm7xx_base_timer = {
.name = "npcm7xx-base-timer",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_TIMER(qtimer, NPCM7xxTimer),
VMSTATE_INT64(expires_ns, NPCM7xxTimer),
VMSTATE_INT64(remaining_ns, NPCM7xxTimer),
VMSTATE_TIMER(qtimer, NPCM7xxBaseTimer),
VMSTATE_INT64(expires_ns, NPCM7xxBaseTimer),
VMSTATE_INT64(remaining_ns, NPCM7xxBaseTimer),
VMSTATE_END_OF_LIST(),
},
};
static const VMStateDescription vmstate_npcm7xx_timer = {
.name = "npcm7xx-timer",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(base_timer, NPCM7xxTimer,
0, vmstate_npcm7xx_base_timer,
NPCM7xxBaseTimer),
VMSTATE_UINT32(tcsr, NPCM7xxTimer),
VMSTATE_UINT32(ticr, NPCM7xxTimer),
VMSTATE_END_OF_LIST(),
},
};
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
.name = "npcm7xx-timer-ctrl",
static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
.name = "npcm7xx-watchdog-timer",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(base_timer, NPCM7xxWatchdogTimer,
0, vmstate_npcm7xx_base_timer,
NPCM7xxBaseTimer),
VMSTATE_UINT32(wtcr, NPCM7xxWatchdogTimer),
VMSTATE_END_OF_LIST(),
},
};
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
.name = "npcm7xx-timer-ctrl",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
VMSTATE_UINT32(wtcr, NPCM7xxTimerCtrlState),
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
NPCM7xxTimer),
VMSTATE_STRUCT(watchdog_timer, NPCM7xxTimerCtrlState,
0, vmstate_npcm7xx_watchdog_timer,
NPCM7xxWatchdogTimer),
VMSTATE_END_OF_LIST(),
},
};

19
hw/usb/hcd-ehci-sysbus.c
View File

@ -147,6 +147,24 @@ static const TypeInfo ehci_aw_h3_type_info = {
.class_init = ehci_aw_h3_class_init,
};
static void ehci_npcm7xx_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
sec->capsbase = 0x0;
sec->opregbase = 0x10;
sec->portscbase = 0x44;
sec->portnr = 1;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
}
static const TypeInfo ehci_npcm7xx_type_info = {
.name = TYPE_NPCM7XX_EHCI,
.parent = TYPE_SYS_BUS_EHCI,
.class_init = ehci_npcm7xx_class_init,
};
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
@ -269,6 +287,7 @@ static void ehci_sysbus_register_types(void)
type_register_static(&ehci_platform_type_info);
type_register_static(&ehci_exynos4210_type_info);
type_register_static(&ehci_aw_h3_type_info);
type_register_static(&ehci_npcm7xx_type_info);
type_register_static(&ehci_tegra2_type_info);
type_register_static(&ehci_ppc4xx_type_info);
type_register_static(&ehci_fusbh200_type_info);

1
hw/usb/hcd-ehci.h
View File

@ -344,6 +344,7 @@ struct EHCIPCIState {
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
#define TYPE_NPCM7XX_EHCI "npcm7xx-ehci-usb"
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"

3
hw/watchdog/Kconfig
View File

@ -17,3 +17,6 @@ config WDT_DIAG288
config WDT_IMX2
bool
config WDT_SBSA
bool

1
hw/watchdog/meson.build
View File

@ -5,3 +5,4 @@ softmmu_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wdt_ib700.c'))
softmmu_ss.add(when: 'CONFIG_WDT_DIAG288', if_true: files('wdt_diag288.c'))
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('wdt_aspeed.c'))
softmmu_ss.add(when: 'CONFIG_WDT_IMX2', if_true: files('wdt_imx2.c'))
softmmu_ss.add(when: 'CONFIG_WDT_SBSA', if_true: files('sbsa_gwdt.c'))

293
hw/watchdog/sbsa_gwdt.c Normal file
View File

@ -0,0 +1,293 @@
/*
* Generic watchdog device model for SBSA
*
* The watchdog device has been implemented as revision 1 variant of
* the ARM SBSA specification v6.0
* (https://developer.arm.com/documentation/den0029/d?lang=en)
*
* Copyright Linaro.org 2020
*
* Authors:
* Shashi Mallela <shashi.mallela@linaro.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or (at your
* option) any later version. See the COPYING file in the top-level directory.
*
*/
#include "qemu/osdep.h"
#include "sysemu/reset.h"
#include "sysemu/watchdog.h"
#include "hw/watchdog/sbsa_gwdt.h"
#include "qemu/timer.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
static WatchdogTimerModel model = {
.wdt_name = TYPE_WDT_SBSA,
.wdt_description = "SBSA-compliant generic watchdog device",
};
static const VMStateDescription vmstate_sbsa_gwdt = {
.name = "sbsa-gwdt",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_TIMER_PTR(timer, SBSA_GWDTState),
VMSTATE_UINT32(wcs, SBSA_GWDTState),
VMSTATE_UINT32(worl, SBSA_GWDTState),
VMSTATE_UINT32(woru, SBSA_GWDTState),
VMSTATE_UINT32(wcvl, SBSA_GWDTState),
VMSTATE_UINT32(wcvu, SBSA_GWDTState),
VMSTATE_END_OF_LIST()
}
};
typedef enum WdtRefreshType {
EXPLICIT_REFRESH = 0,
TIMEOUT_REFRESH = 1,
} WdtRefreshType;
static uint64_t sbsa_gwdt_rread(void *opaque, hwaddr addr, unsigned int size)
{
SBSA_GWDTState *s = SBSA_GWDT(opaque);
uint32_t ret = 0;
switch (addr) {
case SBSA_GWDT_WRR:
/* watch refresh read has no effect and returns 0 */
ret = 0;
break;
case SBSA_GWDT_W_IIDR:
ret = s->id;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "bad address in refresh frame read :"
" 0x%x\n", (int)addr);
}
return ret;
}
static uint64_t sbsa_gwdt_read(void *opaque, hwaddr addr, unsigned int size)
{
SBSA_GWDTState *s = SBSA_GWDT(opaque);
uint32_t ret = 0;
switch (addr) {
case SBSA_GWDT_WCS:
ret = s->wcs;
break;
case SBSA_GWDT_WOR:
ret = s->worl;
break;
case SBSA_GWDT_WORU:
ret = s->woru;
break;
case SBSA_GWDT_WCV:
ret = s->wcvl;
break;
case SBSA_GWDT_WCVU:
ret = s->wcvu;
break;
case SBSA_GWDT_W_IIDR:
ret = s->id;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "bad address in control frame read :"
" 0x%x\n", (int)addr);
}
return ret;
}
static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype)
{
uint64_t timeout = 0;
timer_del(s->timer);
if (s->wcs & SBSA_GWDT_WCS_EN) {
/*
* Extract the upper 16 bits from woru & 32 bits from worl
* registers to construct the 48 bit offset value
*/
timeout = s->woru;
timeout <<= 32;
timeout |= s->worl;
timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ);
timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) &&
(!(s->wcs & SBSA_GWDT_WCS_WS0)))) {
/* store the current timeout value into compare registers */
s->wcvu = timeout >> 32;
s->wcvl = timeout;
}
timer_mod(s->timer, timeout);
}
}
static void sbsa_gwdt_rwrite(void *opaque, hwaddr offset, uint64_t data,
unsigned size) {
SBSA_GWDTState *s = SBSA_GWDT(opaque);
if (offset == SBSA_GWDT_WRR) {
s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "bad address in refresh frame write :"
" 0x%x\n", (int)offset);
}
}
static void sbsa_gwdt_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size) {
SBSA_GWDTState *s = SBSA_GWDT(opaque);
switch (offset) {
case SBSA_GWDT_WCS:
s->wcs = data & SBSA_GWDT_WCS_EN;
qemu_set_irq(s->irq, 0);
sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
break;
case SBSA_GWDT_WOR:
s->worl = data;
s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
qemu_set_irq(s->irq, 0);
sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
break;
case SBSA_GWDT_WORU:
s->woru = data & SBSA_GWDT_WOR_MASK;
s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
qemu_set_irq(s->irq, 0);
sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
break;
case SBSA_GWDT_WCV:
s->wcvl = data;
break;
case SBSA_GWDT_WCVU:
s->wcvu = data;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "bad address in control frame write :"
" 0x%x\n", (int)offset);
}
return;
}
static void wdt_sbsa_gwdt_reset(DeviceState *dev)
{
SBSA_GWDTState *s = SBSA_GWDT(dev);
timer_del(s->timer);
s->wcs = 0;
s->wcvl = 0;
s->wcvu = 0;
s->worl = 0;
s->woru = 0;
s->id = SBSA_GWDT_ID;
}
static void sbsa_gwdt_timer_sysinterrupt(void *opaque)
{
SBSA_GWDTState *s = SBSA_GWDT(opaque);
if (!(s->wcs & SBSA_GWDT_WCS_WS0)) {
s->wcs |= SBSA_GWDT_WCS_WS0;
sbsa_gwdt_update_timer(s, TIMEOUT_REFRESH);
qemu_set_irq(s->irq, 1);
} else {
s->wcs |= SBSA_GWDT_WCS_WS1;
qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
/*
* Reset the watchdog only if the guest gets notified about
* expiry. watchdog_perform_action() may temporarily relinquish
* the BQL; reset before triggering the action to avoid races with
* sbsa_gwdt instructions.
*/
switch (get_watchdog_action()) {
case WATCHDOG_ACTION_DEBUG:
case WATCHDOG_ACTION_NONE:
case WATCHDOG_ACTION_PAUSE:
break;
default:
wdt_sbsa_gwdt_reset(DEVICE(s));
}
watchdog_perform_action();
}
}
static const MemoryRegionOps sbsa_gwdt_rops = {
.read = sbsa_gwdt_rread,
.write = sbsa_gwdt_rwrite,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
.valid.unaligned = false,
};
static const MemoryRegionOps sbsa_gwdt_ops = {
.read = sbsa_gwdt_read,
.write = sbsa_gwdt_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
.valid.unaligned = false,
};
static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp)
{
SBSA_GWDTState *s = SBSA_GWDT(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
memory_region_init_io(&s->rmmio, OBJECT(dev),
&sbsa_gwdt_rops, s,
"sbsa_gwdt.refresh",
SBSA_GWDT_RMMIO_SIZE);
memory_region_init_io(&s->cmmio, OBJECT(dev),
&sbsa_gwdt_ops, s,
"sbsa_gwdt.control",
SBSA_GWDT_CMMIO_SIZE);
sysbus_init_mmio(sbd, &s->rmmio);
sysbus_init_mmio(sbd, &s->cmmio);
sysbus_init_irq(sbd, &s->irq);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sbsa_gwdt_timer_sysinterrupt,
dev);
}
static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = wdt_sbsa_gwdt_realize;
dc->reset = wdt_sbsa_gwdt_reset;
dc->hotpluggable = false;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->vmsd = &vmstate_sbsa_gwdt;
}
static const TypeInfo wdt_sbsa_gwdt_info = {
.class_init = wdt_sbsa_gwdt_class_init,
.parent = TYPE_SYS_BUS_DEVICE,
.name = TYPE_WDT_SBSA,
.instance_size = sizeof(SBSA_GWDTState),
};
static void wdt_sbsa_gwdt_register_types(void)
{
watchdog_add_model(&model);
type_register_static(&wdt_sbsa_gwdt_info);
}
type_init(wdt_sbsa_gwdt_register_types)

22
include/elf.h
View File

@ -26,9 +26,13 @@ typedef int64_t Elf64_Sxword;
#define PT_NOTE 4
#define PT_SHLIB 5
#define PT_PHDR 6
#define PT_LOOS 0x60000000
#define PT_HIOS 0x6fffffff
#define PT_LOPROC 0x70000000
#define PT_HIPROC 0x7fffffff
#define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
#define PT_MIPS_REGINFO 0x70000000
#define PT_MIPS_RTPROC 0x70000001
#define PT_MIPS_OPTIONS 0x70000002
@ -1659,6 +1663,24 @@ typedef struct elf64_shdr {
#define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */
#define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension regs */
/* Defined note types for GNU systems. */
#define NT_GNU_PROPERTY_TYPE_0 5 /* Program property */
/* Values used in GNU .note.gnu.property notes (NT_GNU_PROPERTY_TYPE_0). */
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
#define GNU_PROPERTY_LOPROC 0xc0000000
#define GNU_PROPERTY_HIPROC 0xdfffffff
#define GNU_PROPERTY_LOUSER 0xe0000000
#define GNU_PROPERTY_HIUSER 0xffffffff
#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1u << 0)
#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1u << 1)
/*
* Physical entry point into the kernel.
*

2
include/exec/cpu-all.h
View File

@ -274,6 +274,8 @@ extern intptr_t qemu_host_page_mask;
/* FIXME: Code that sets/uses this is broken and needs to go away. */
#define PAGE_RESERVED 0x0020
#endif
/* Target-specific bits that will be used via page_get_flags(). */
#define PAGE_TARGET_1 0x0080
#if defined(CONFIG_USER_ONLY)
void page_dump(FILE *f);

5
include/hw/arm/bcm2835_peripherals.h
View File

@ -23,6 +23,7 @@
#include "hw/misc/bcm2835_mbox.h"
#include "hw/misc/bcm2835_mphi.h"
#include "hw/misc/bcm2835_thermal.h"
#include "hw/misc/bcm2835_cprman.h"
#include "hw/sd/sdhci.h"
#include "hw/sd/bcm2835_sdhost.h"
#include "hw/gpio/bcm2835_gpio.h"
@ -47,8 +48,8 @@ struct BCM2835PeripheralState {
BCM2835MphiState mphi;
UnimplementedDeviceState txp;
UnimplementedDeviceState armtmr;
UnimplementedDeviceState cprman;
UnimplementedDeviceState a2w;
UnimplementedDeviceState powermgt;
BCM2835CprmanState cprman;
PL011State uart0;
BCM2835AuxState aux;
BCM2835FBState fb;

9
include/hw/arm/bcm2836.h
View File

@ -26,6 +26,7 @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
* them, code using these devices should always handle them via the
* BCM283x base class, so they have no BCM2836(obj) etc macros.
*/
#define TYPE_BCM2835 "bcm2835"
#define TYPE_BCM2836 "bcm2836"
#define TYPE_BCM2837 "bcm2837"
@ -43,12 +44,4 @@ struct BCM283XState {
BCM2835PeripheralState peripherals;
};
typedef struct BCM283XInfo BCM283XInfo;
struct BCM283XClass {
DeviceClass parent_class;
const BCM283XInfo *info;
};
#endif /* BCM2836_H */

8
include/hw/arm/npcm7xx.h
View File

@ -18,12 +18,16 @@
#include "hw/boards.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/gpio/npcm7xx_gpio.h"
#include "hw/mem/npcm7xx_mc.h"
#include "hw/misc/npcm7xx_clk.h"
#include "hw/misc/npcm7xx_gcr.h"
#include "hw/misc/npcm7xx_rng.h"
#include "hw/nvram/npcm7xx_otp.h"
#include "hw/timer/npcm7xx_timer.h"
#include "hw/ssi/npcm7xx_fiu.h"
#include "hw/usb/hcd-ehci.h"
#include "hw/usb/hcd-ohci.h"
#include "target/arm/cpu.h"
#define NPCM7XX_MAX_NUM_CPUS (2)
@ -75,6 +79,10 @@ typedef struct NPCM7xxState {
NPCM7xxOTPState key_storage;
NPCM7xxOTPState fuse_array;
NPCM7xxMCState mc;
NPCM7xxRNGState rng;
NPCM7xxGPIOState gpio[8];
EHCISysBusState ehci;
OHCISysBusState ohci;
NPCM7xxFIUState fiu[2];
} NPCM7xxState;

5
include/hw/arm/raspi_platform.h
View File

@ -45,9 +45,8 @@
#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
* Doorbells & Mailboxes */
#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */
#define CM_OFFSET 0x101000 /* Clock Management */
#define A2W_OFFSET 0x102000 /* Reset controller */
#define PM_OFFSET 0x100000 /* Power Management */
#define CPRMAN_OFFSET 0x101000 /* Clock Management */
#define AVS_OFFSET 0x103000 /* Audio Video Standard */
#define RNG_OFFSET 0x104000
#define GPIO_OFFSET 0x200000

1
include/hw/char/pl011.h
View File

@ -49,6 +49,7 @@ struct PL011State {
int read_trigger;
CharBackend chr;
qemu_irq irq[6];
Clock *clk;
const unsigned char *id;
};

5
include/hw/clock.h
View File

@ -81,6 +81,11 @@ extern const VMStateDescription vmstate_clock;
VMSTATE_CLOCK_V(field, state, 0)
#define VMSTATE_CLOCK_V(field, state, version) \
VMSTATE_STRUCT_POINTER_V(field, state, version, vmstate_clock, Clock)
#define VMSTATE_ARRAY_CLOCK(field, state, num) \
VMSTATE_ARRAY_CLOCK_V(field, state, num, 0)
#define VMSTATE_ARRAY_CLOCK_V(field, state, num, version) \
VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(field, state, num, version, \
vmstate_clock, Clock)
/**
* clock_setup_canonical_path:

55
include/hw/gpio/npcm7xx_gpio.h Normal file
View File

@ -0,0 +1,55 @@
/*
* Nuvoton NPCM7xx General Purpose Input / Output (GPIO)
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef NPCM7XX_GPIO_H
#define NPCM7XX_GPIO_H
#include "exec/memory.h"
#include "hw/sysbus.h"
/* Number of pins managed by each controller. */
#define NPCM7XX_GPIO_NR_PINS (32)
/*
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.
*/
#define NPCM7XX_GPIO_NR_REGS (0x80 / sizeof(uint32_t))
typedef struct NPCM7xxGPIOState {
SysBusDevice parent;
/* Properties to be defined by the SoC */
uint32_t reset_pu;
uint32_t reset_pd;
uint32_t reset_osrc;
uint32_t reset_odsc;
MemoryRegion mmio;
qemu_irq irq;
qemu_irq output[NPCM7XX_GPIO_NR_PINS];
uint32_t pin_level;
uint32_t ext_level;
uint32_t ext_driven;
uint32_t regs[NPCM7XX_GPIO_NR_REGS];
} NPCM7xxGPIOState;
#define TYPE_NPCM7XX_GPIO "npcm7xx-gpio"
#define NPCM7XX_GPIO(obj) \
OBJECT_CHECK(NPCM7xxGPIOState, (obj), TYPE_NPCM7XX_GPIO)
#endif /* NPCM7XX_GPIO_H */

210
include/hw/misc/bcm2835_cprman.h Normal file
View File

@ -0,0 +1,210 @@
/*
* BCM2835 CPRMAN clock manager
*
* Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_MISC_CPRMAN_H
#define HW_MISC_CPRMAN_H
#include "hw/sysbus.h"
#include "hw/qdev-clock.h"
#define TYPE_BCM2835_CPRMAN "bcm2835-cprman"
typedef struct BCM2835CprmanState BCM2835CprmanState;
DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN,
TYPE_BCM2835_CPRMAN)
#define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t))
typedef enum CprmanPll {
CPRMAN_PLLA = 0,
CPRMAN_PLLC,
CPRMAN_PLLD,
CPRMAN_PLLH,
CPRMAN_PLLB,
CPRMAN_NUM_PLL
} CprmanPll;
typedef enum CprmanPllChannel {
CPRMAN_PLLA_CHANNEL_DSI0 = 0,
CPRMAN_PLLA_CHANNEL_CORE,
CPRMAN_PLLA_CHANNEL_PER,
CPRMAN_PLLA_CHANNEL_CCP2,
CPRMAN_PLLC_CHANNEL_CORE2,
CPRMAN_PLLC_CHANNEL_CORE1,
CPRMAN_PLLC_CHANNEL_PER,
CPRMAN_PLLC_CHANNEL_CORE0,
CPRMAN_PLLD_CHANNEL_DSI0,
CPRMAN_PLLD_CHANNEL_CORE,
CPRMAN_PLLD_CHANNEL_PER,
CPRMAN_PLLD_CHANNEL_DSI1,
CPRMAN_PLLH_CHANNEL_AUX,
CPRMAN_PLLH_CHANNEL_RCAL,
CPRMAN_PLLH_CHANNEL_PIX,
CPRMAN_PLLB_CHANNEL_ARM,
CPRMAN_NUM_PLL_CHANNEL,
/* Special values used when connecting clock sources to clocks */
CPRMAN_CLOCK_SRC_NORMAL = -1,
CPRMAN_CLOCK_SRC_FORCE_GROUND = -2,
CPRMAN_CLOCK_SRC_DSI0HSCK = -3,
} CprmanPllChannel;
typedef enum CprmanClockMux {
CPRMAN_CLOCK_GNRIC,
CPRMAN_CLOCK_VPU,
CPRMAN_CLOCK_SYS,
CPRMAN_CLOCK_PERIA,
CPRMAN_CLOCK_PERII,
CPRMAN_CLOCK_H264,
CPRMAN_CLOCK_ISP,
CPRMAN_CLOCK_V3D,
CPRMAN_CLOCK_CAM0,
CPRMAN_CLOCK_CAM1,
CPRMAN_CLOCK_CCP2,
CPRMAN_CLOCK_DSI0E,
CPRMAN_CLOCK_DSI0P,
CPRMAN_CLOCK_DPI,
CPRMAN_CLOCK_GP0,
CPRMAN_CLOCK_GP1,
CPRMAN_CLOCK_GP2,
CPRMAN_CLOCK_HSM,
CPRMAN_CLOCK_OTP,
CPRMAN_CLOCK_PCM,
CPRMAN_CLOCK_PWM,
CPRMAN_CLOCK_SLIM,
CPRMAN_CLOCK_SMI,
CPRMAN_CLOCK_TEC,
CPRMAN_CLOCK_TD0,
CPRMAN_CLOCK_TD1,
CPRMAN_CLOCK_TSENS,
CPRMAN_CLOCK_TIMER,
CPRMAN_CLOCK_UART,
CPRMAN_CLOCK_VEC,
CPRMAN_CLOCK_PULSE,
CPRMAN_CLOCK_SDC,
CPRMAN_CLOCK_ARM,
CPRMAN_CLOCK_AVEO,
CPRMAN_CLOCK_EMMC,
CPRMAN_CLOCK_EMMC2,
CPRMAN_NUM_CLOCK_MUX
} CprmanClockMux;
typedef enum CprmanClockMuxSource {
CPRMAN_CLOCK_SRC_GND = 0,
CPRMAN_CLOCK_SRC_XOSC,
CPRMAN_CLOCK_SRC_TD0,
CPRMAN_CLOCK_SRC_TD1,
CPRMAN_CLOCK_SRC_PLLA,
CPRMAN_CLOCK_SRC_PLLC,
CPRMAN_CLOCK_SRC_PLLD,
CPRMAN_CLOCK_SRC_PLLH,
CPRMAN_CLOCK_SRC_PLLC_CORE1,
CPRMAN_CLOCK_SRC_PLLC_CORE2,
CPRMAN_NUM_CLOCK_MUX_SRC
} CprmanClockMuxSource;
typedef struct CprmanPllState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
CprmanPll id;
uint32_t *reg_cm;
uint32_t *reg_a2w_ctrl;
uint32_t *reg_a2w_ana; /* ANA[0] .. ANA[3] */
uint32_t prediv_mask; /* prediv bit in ana[1] */
uint32_t *reg_a2w_frac;
Clock *xosc_in;
Clock *out;
} CprmanPllState;
typedef struct CprmanPllChannelState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
CprmanPllChannel id;
CprmanPll parent;
uint32_t *reg_cm;
uint32_t hold_mask;
uint32_t load_mask;
uint32_t *reg_a2w_ctrl;
int fixed_divider;
Clock *pll_in;
Clock *out;
} CprmanPllChannelState;
typedef struct CprmanClockMuxState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
CprmanClockMux id;
uint32_t *reg_ctl;
uint32_t *reg_div;
int int_bits;
int frac_bits;
Clock *srcs[CPRMAN_NUM_CLOCK_MUX_SRC];
Clock *out;
/*
* Used by clock srcs update callback to retrieve both the clock and the
* source number.
*/
struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
} CprmanClockMuxState;
typedef struct CprmanDsi0HsckMuxState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
CprmanClockMux id;
uint32_t *reg_cm;
Clock *plla_in;
Clock *plld_in;
Clock *out;
} CprmanDsi0HsckMuxState;
struct BCM2835CprmanState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
CprmanPllState plls[CPRMAN_NUM_PLL];
CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
CprmanDsi0HsckMuxState dsi0hsck_mux;
uint32_t regs[CPRMAN_NUM_REGS];
uint32_t xosc_freq;
Clock *xosc;
Clock *gnd;
};
#endif

1019
include/hw/misc/bcm2835_cprman_internals.h Normal file
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File diff suppressed because it is too large Load Diff

2
include/hw/misc/npcm7xx_clk.h
View File

@ -31,6 +31,8 @@
*/
#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
typedef struct NPCM7xxCLKState {
SysBusDevice parent;

34
include/hw/misc/npcm7xx_rng.h Normal file
View File

@ -0,0 +1,34 @@
/*
* Nuvoton NPCM7xx Random Number Generator.
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef NPCM7XX_RNG_H
#define NPCM7XX_RNG_H
#include "hw/sysbus.h"
typedef struct NPCM7xxRNGState {
SysBusDevice parent;
MemoryRegion iomem;
uint8_t rngcs;
uint8_t rngd;
uint8_t rngmode;
} NPCM7xxRNGState;
#define TYPE_NPCM7XX_RNG "npcm7xx-rng"
#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
#endif /* NPCM7XX_RNG_H */

3
include/hw/timer/armv7m_systick.h
View File

@ -14,6 +14,7 @@
#include "hw/sysbus.h"
#include "qom/object.h"
#include "hw/ptimer.h"
#define TYPE_SYSTICK "armv7m_systick"
@ -27,7 +28,7 @@ struct SysTickState {
uint32_t control;
uint32_t reload;
int64_t tick;
QEMUTimer *timer;
ptimer_state *ptimer;
MemoryRegion iomem;
qemu_irq irq;
};

48
include/hw/timer/npcm7xx_timer.h
View File

@ -29,14 +29,31 @@
*/
#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
/* The basic watchdog timer period is 2^14 clock cycles. */
#define NPCM7XX_WATCHDOG_BASETIME_SHIFT 14
#define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
/**
* struct NPCM7xxTimer - Individual timer state.
* @irq: GIC interrupt line to fire on expiration (if enabled).
* struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
* watchdog timer use.
* @qtimer: QEMU timer that notifies us on expiration.
* @expires_ns: Absolute virtual expiration time.
* @remaining_ns: Remaining time until expiration if timer is paused.
*/
typedef struct NPCM7xxBaseTimer {
QEMUTimer qtimer;
int64_t expires_ns;
int64_t remaining_ns;
} NPCM7xxBaseTimer;
/**
* struct NPCM7xxTimer - Individual timer state.
* @ctrl: The timer module that owns this timer.
* @irq: GIC interrupt line to fire on expiration (if enabled).
* @base_timer: The basic timer functionality for this timer.
* @tcsr: The Timer Control and Status Register.
* @ticr: The Timer Initial Count Register.
*/
@ -44,21 +61,38 @@ typedef struct NPCM7xxTimer {
NPCM7xxTimerCtrlState *ctrl;
qemu_irq irq;
QEMUTimer qtimer;
int64_t expires_ns;
int64_t remaining_ns;
NPCM7xxBaseTimer base_timer;
uint32_t tcsr;
uint32_t ticr;
} NPCM7xxTimer;
/**
* struct NPCM7xxWatchdogTimer - The watchdog timer state.
* @ctrl: The timer module that owns this timer.
* @irq: GIC interrupt line to fire on expiration (if enabled).
* @reset_signal: The GPIO used to send a reset signal.
* @base_timer: The basic timer functionality for this timer.
* @wtcr: The Watchdog Timer Control Register.
*/
typedef struct NPCM7xxWatchdogTimer {
NPCM7xxTimerCtrlState *ctrl;
qemu_irq irq;
qemu_irq reset_signal;
NPCM7xxBaseTimer base_timer;
uint32_t wtcr;
} NPCM7xxWatchdogTimer;
/**
* struct NPCM7xxTimerCtrlState - Timer Module device state.
* @parent: System bus device.
* @iomem: Memory region through which registers are accessed.
* @index: The index of this timer module.
* @tisr: The Timer Interrupt Status Register.
* @wtcr: The Watchdog Timer Control Register.
* @timer: The five individual timers managed by this module.
* @watchdog_timer: The watchdog timer managed by this module.
*/
struct NPCM7xxTimerCtrlState {
SysBusDevice parent;
@ -66,9 +100,9 @@ struct NPCM7xxTimerCtrlState {
MemoryRegion iomem;
uint32_t tisr;
uint32_t wtcr;
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
NPCM7xxWatchdogTimer watchdog_timer;
};
#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"

79
include/hw/watchdog/sbsa_gwdt.h Normal file
View File

@ -0,0 +1,79 @@
/*
* Copyright (c) 2020 Linaro Limited
*
* Authors:
* Shashi Mallela <shashi.mallela@linaro.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or (at your
* option) any later version. See the COPYING file in the top-level directory.
*
*/
#ifndef WDT_SBSA_GWDT_H
#define WDT_SBSA_GWDT_H
#include "qemu/bitops.h"
#include "hw/sysbus.h"
#include "hw/irq.h"
#define TYPE_WDT_SBSA "sbsa_gwdt"
#define SBSA_GWDT(obj) \
OBJECT_CHECK(SBSA_GWDTState, (obj), TYPE_WDT_SBSA)
#define SBSA_GWDT_CLASS(klass) \
OBJECT_CLASS_CHECK(SBSA_GWDTClass, (klass), TYPE_WDT_SBSA)
#define SBSA_GWDT_GET_CLASS(obj) \
OBJECT_GET_CLASS(SBSA_GWDTClass, (obj), TYPE_WDT_SBSA)
/* SBSA Generic Watchdog register definitions */
/* refresh frame */
#define SBSA_GWDT_WRR 0x000
/* control frame */
#define SBSA_GWDT_WCS 0x000
#define SBSA_GWDT_WOR 0x008
#define SBSA_GWDT_WORU 0x00C
#define SBSA_GWDT_WCV 0x010
#define SBSA_GWDT_WCVU 0x014
/* Watchdog Interface Identification Register */
#define SBSA_GWDT_W_IIDR 0xFCC
/* Watchdog Control and Status Register Bits */
#define SBSA_GWDT_WCS_EN BIT(0)
#define SBSA_GWDT_WCS_WS0 BIT(1)
#define SBSA_GWDT_WCS_WS1 BIT(2)
#define SBSA_GWDT_WOR_MASK 0x0000FFFF
/*
* Watchdog Interface Identification Register definition
* considering JEP106 code for ARM in Bits [11:0]
*/
#define SBSA_GWDT_ID 0x1043B
/* 2 Separate memory regions for each of refresh & control register frames */
#define SBSA_GWDT_RMMIO_SIZE 0x1000
#define SBSA_GWDT_CMMIO_SIZE 0x1000
#define SBSA_TIMER_FREQ 62500000 /* Hz */
typedef struct SBSA_GWDTState {
/* <private> */
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion rmmio;
MemoryRegion cmmio;
qemu_irq irq;
QEMUTimer *timer;
uint32_t id;
uint32_t wcs;
uint32_t worl;
uint32_t woru;
uint32_t wcvl;
uint32_t wcvu;
} SBSA_GWDTState;
#endif /* WDT_SBSA_GWDT_H */

10
linux-user/aarch64/signal.c
View File

@ -506,10 +506,16 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
+ offsetof(struct target_rt_frame_record, tramp);
}
env->xregs[0] = usig;
env->xregs[31] = frame_addr;
env->xregs[29] = frame_addr + fr_ofs;
env->pc = ka->_sa_handler;
env->xregs[30] = return_addr;
env->xregs[31] = frame_addr;
env->pc = ka->_sa_handler;
/* Invoke the signal handler as if by indirect call. */
if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
env->btype = 2;
}
if (info) {
tswap_siginfo(&frame->info, info);
env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);

326
linux-user/elfload.c
View File

@ -12,6 +12,7 @@
#include "qemu/guest-random.h"
#include "qemu/units.h"
#include "qemu/selfmap.h"
#include "qapi/error.h"
#ifdef _ARCH_PPC64
#undef ARCH_DLINFO
@ -1521,6 +1522,39 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
#include "elf.h"
/* We must delay the following stanzas until after "elf.h". */
#if defined(TARGET_AARCH64)
static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
const uint32_t *data,
struct image_info *info,
Error **errp)
{
if (pr_type == GNU_PROPERTY_AARCH64_FEATURE_1_AND) {
if (pr_datasz != sizeof(uint32_t)) {
error_setg(errp, "Ill-formed GNU_PROPERTY_AARCH64_FEATURE_1_AND");
return false;
}
/* We will extract GNU_PROPERTY_AARCH64_FEATURE_1_BTI later. */
info->note_flags = *data;
}
return true;
}
#define ARCH_USE_GNU_PROPERTY 1
#else
static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
const uint32_t *data,
struct image_info *info,
Error **errp)
{
g_assert_not_reached();
}
#define ARCH_USE_GNU_PROPERTY 0
#endif
struct exec
{
unsigned int a_info; /* Use macros N_MAGIC, etc for access */
@ -2372,6 +2406,150 @@ void probe_guest_base(const char *image_name, abi_ulong guest_loaddr,
"@ 0x%" PRIx64 "\n", (uint64_t)guest_base);
}
enum {
/* The string "GNU\0" as a magic number. */
GNU0_MAGIC = const_le32('G' | 'N' << 8 | 'U' << 16),
NOTE_DATA_SZ = 1 * KiB,
NOTE_NAME_SZ = 4,
ELF_GNU_PROPERTY_ALIGN = ELF_CLASS == ELFCLASS32 ? 4 : 8,
};
/*
* Process a single gnu_property entry.
* Return false for error.
*/
static bool parse_elf_property(const uint32_t *data, int *off, int datasz,
struct image_info *info, bool have_prev_type,
uint32_t *prev_type, Error **errp)
{
uint32_t pr_type, pr_datasz, step;
if (*off > datasz || !QEMU_IS_ALIGNED(*off, ELF_GNU_PROPERTY_ALIGN)) {
goto error_data;
}
datasz -= *off;
data += *off / sizeof(uint32_t);
if (datasz < 2 * sizeof(uint32_t)) {
goto error_data;
}
pr_type = data[0];
pr_datasz = data[1];
data += 2;
datasz -= 2 * sizeof(uint32_t);
step = ROUND_UP(pr_datasz, ELF_GNU_PROPERTY_ALIGN);
if (step > datasz) {
goto error_data;
}
/* Properties are supposed to be unique and sorted on pr_type. */
if (have_prev_type && pr_type <= *prev_type) {
if (pr_type == *prev_type) {
error_setg(errp, "Duplicate property in PT_GNU_PROPERTY");
} else {
error_setg(errp, "Unsorted property in PT_GNU_PROPERTY");
}
return false;
}
*prev_type = pr_type;
if (!arch_parse_elf_property(pr_type, pr_datasz, data, info, errp)) {
return false;
}
*off += 2 * sizeof(uint32_t) + step;
return true;
error_data:
error_setg(errp, "Ill-formed property in PT_GNU_PROPERTY");
return false;
}
/* Process NT_GNU_PROPERTY_TYPE_0. */
static bool parse_elf_properties(int image_fd,
struct image_info *info,
const struct elf_phdr *phdr,
char bprm_buf[BPRM_BUF_SIZE],
Error **errp)
{
union {
struct elf_note nhdr;
uint32_t data[NOTE_DATA_SZ / sizeof(uint32_t)];
} note;
int n, off, datasz;
bool have_prev_type;
uint32_t prev_type;
/* Unless the arch requires properties, ignore them. */
if (!ARCH_USE_GNU_PROPERTY) {
return true;
}
/* If the properties are crazy large, that's too bad. */
n = phdr->p_filesz;
if (n > sizeof(note)) {
error_setg(errp, "PT_GNU_PROPERTY too large");
return false;
}
if (n < sizeof(note.nhdr)) {
error_setg(errp, "PT_GNU_PROPERTY too small");
return false;
}
if (phdr->p_offset + n <= BPRM_BUF_SIZE) {
memcpy(&note, bprm_buf + phdr->p_offset, n);
} else {
ssize_t len = pread(image_fd, &note, n, phdr->p_offset);
if (len != n) {
error_setg_errno(errp, errno, "Error reading file header");
return false;
}
}
/*
* The contents of a valid PT_GNU_PROPERTY is a sequence
* of uint32_t -- swap them all now.
*/
#ifdef BSWAP_NEEDED
for (int i = 0; i < n / 4; i++) {
bswap32s(note.data + i);
}
#endif
/*
* Note that nhdr is 3 words, and that the "name" described by namesz
* immediately follows nhdr and is thus at the 4th word. Further, all
* of the inputs to the kernel's round_up are multiples of 4.
*/
if (note.nhdr.n_type != NT_GNU_PROPERTY_TYPE_0 ||
note.nhdr.n_namesz != NOTE_NAME_SZ ||
note.data[3] != GNU0_MAGIC) {
error_setg(errp, "Invalid note in PT_GNU_PROPERTY");
return false;
}
off = sizeof(note.nhdr) + NOTE_NAME_SZ;
datasz = note.nhdr.n_descsz + off;
if (datasz > n) {
error_setg(errp, "Invalid note size in PT_GNU_PROPERTY");
return false;
}
have_prev_type = false;
prev_type = 0;
while (1) {
if (off == datasz) {
return true; /* end, exit ok */
}
if (!parse_elf_property(note.data, &off, datasz, info,
have_prev_type, &prev_type, errp)) {
return false;
}
have_prev_type = true;
}
}
/* Load an ELF image into the address space.
IMAGE_NAME is the filename of the image, to use in error messages.
@ -2391,16 +2569,17 @@ static void load_elf_image(const char *image_name, int image_fd,
struct elfhdr *ehdr = (struct elfhdr *)bprm_buf;
struct elf_phdr *phdr;
abi_ulong load_addr, load_bias, loaddr, hiaddr, error;
int i, retval;
const char *errmsg;
int i, retval, prot_exec;
Error *err = NULL;
/* First of all, some simple consistency checks */
errmsg = "Invalid ELF image for this architecture";
if (!elf_check_ident(ehdr)) {
error_setg(&err, "Invalid ELF image for this architecture");
goto exit_errmsg;
}
bswap_ehdr(ehdr);
if (!elf_check_ehdr(ehdr)) {
error_setg(&err, "Invalid ELF image for this architecture");
goto exit_errmsg;
}
@ -2421,22 +2600,54 @@ static void load_elf_image(const char *image_name, int image_fd,
mmap_lock();
/* Find the maximum size of the image and allocate an appropriate
amount of memory to handle that. */
/*
* Find the maximum size of the image and allocate an appropriate
* amount of memory to handle that. Locate the interpreter, if any.
*/
loaddr = -1, hiaddr = 0;
info->alignment = 0;
for (i = 0; i < ehdr->e_phnum; ++i) {
if (phdr[i].p_type == PT_LOAD) {
abi_ulong a = phdr[i].p_vaddr - phdr[i].p_offset;
struct elf_phdr *eppnt = phdr + i;
if (eppnt->p_type == PT_LOAD) {
abi_ulong a = eppnt->p_vaddr - eppnt->p_offset;
if (a < loaddr) {
loaddr = a;
}
a = phdr[i].p_vaddr + phdr[i].p_memsz;
a = eppnt->p_vaddr + eppnt->p_memsz;
if (a > hiaddr) {
hiaddr = a;
}
++info->nsegs;
info->alignment |= phdr[i].p_align;
info->alignment |= eppnt->p_align;
} else if (eppnt->p_type == PT_INTERP && pinterp_name) {
g_autofree char *interp_name = NULL;
if (*pinterp_name) {
error_setg(&err, "Multiple PT_INTERP entries");
goto exit_errmsg;
}
interp_name = g_malloc(eppnt->p_filesz);
if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
memcpy(interp_name, bprm_buf + eppnt->p_offset,
eppnt->p_filesz);
} else {
retval = pread(image_fd, interp_name, eppnt->p_filesz,
eppnt->p_offset);
if (retval != eppnt->p_filesz) {
goto exit_read;
}
}
if (interp_name[eppnt->p_filesz - 1] != 0) {
error_setg(&err, "Invalid PT_INTERP entry");
goto exit_errmsg;
}
*pinterp_name = g_steal_pointer(&interp_name);
} else if (eppnt->p_type == PT_GNU_PROPERTY) {
if (!parse_elf_properties(image_fd, info, eppnt, bprm_buf, &err)) {
goto exit_errmsg;
}
}
}
@ -2490,7 +2701,7 @@ static void load_elf_image(const char *image_name, int image_fd,
(ehdr->e_type == ET_EXEC ? MAP_FIXED : 0),
-1, 0);
if (load_addr == -1) {
goto exit_perror;
goto exit_mmap;
}
load_bias = load_addr - loaddr;
@ -2525,15 +2736,41 @@ static void load_elf_image(const char *image_name, int image_fd,
info->brk = 0;
info->elf_flags = ehdr->e_flags;
prot_exec = PROT_EXEC;
#ifdef TARGET_AARCH64
/*
* If the BTI feature is present, this indicates that the executable
* pages of the startup binary should be mapped with PROT_BTI, so that
* branch targets are enforced.
*
* The startup binary is either the interpreter or the static executable.
* The interpreter is responsible for all pages of a dynamic executable.
*
* Elf notes are backward compatible to older cpus.
* Do not enable BTI unless it is supported.
*/
if ((info->note_flags & GNU_PROPERTY_AARCH64_FEATURE_1_BTI)
&& (pinterp_name == NULL || *pinterp_name == 0)
&& cpu_isar_feature(aa64_bti, ARM_CPU(thread_cpu))) {
prot_exec |= TARGET_PROT_BTI;
}
#endif
for (i = 0; i < ehdr->e_phnum; i++) {
struct elf_phdr *eppnt = phdr + i;
if (eppnt->p_type == PT_LOAD) {
abi_ulong vaddr, vaddr_po, vaddr_ps, vaddr_ef, vaddr_em, vaddr_len;
int elf_prot = 0;
if (eppnt->p_flags & PF_R) elf_prot = PROT_READ;
if (eppnt->p_flags & PF_W) elf_prot |= PROT_WRITE;
if (eppnt->p_flags & PF_X) elf_prot |= PROT_EXEC;
if (eppnt->p_flags & PF_R) {
elf_prot |= PROT_READ;
}
if (eppnt->p_flags & PF_W) {
elf_prot |= PROT_WRITE;
}
if (eppnt->p_flags & PF_X) {
elf_prot |= prot_exec;
}
vaddr = load_bias + eppnt->p_vaddr;
vaddr_po = TARGET_ELF_PAGEOFFSET(vaddr);
@ -2551,7 +2788,7 @@ static void load_elf_image(const char *image_name, int image_fd,
image_fd, eppnt->p_offset - vaddr_po);
if (error == -1) {
goto exit_perror;
goto exit_mmap;
}
}
@ -2583,38 +2820,11 @@ static void load_elf_image(const char *image_name, int image_fd,
if (vaddr_em > info->brk) {
info->brk = vaddr_em;
}
} else if (eppnt->p_type == PT_INTERP && pinterp_name) {
char *interp_name;
if (*pinterp_name) {
errmsg = "Multiple PT_INTERP entries";
goto exit_errmsg;
}
interp_name = malloc(eppnt->p_filesz);
if (!interp_name) {
goto exit_perror;
}
if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
memcpy(interp_name, bprm_buf + eppnt->p_offset,
eppnt->p_filesz);
} else {
retval = pread(image_fd, interp_name, eppnt->p_filesz,
eppnt->p_offset);
if (retval != eppnt->p_filesz) {
goto exit_perror;
}
}
if (interp_name[eppnt->p_filesz - 1] != 0) {
errmsg = "Invalid PT_INTERP entry";
goto exit_errmsg;
}
*pinterp_name = interp_name;
#ifdef TARGET_MIPS
} else if (eppnt->p_type == PT_MIPS_ABIFLAGS) {
Mips_elf_abiflags_v0 abiflags;
if (eppnt->p_filesz < sizeof(Mips_elf_abiflags_v0)) {
errmsg = "Invalid PT_MIPS_ABIFLAGS entry";
error_setg(&err, "Invalid PT_MIPS_ABIFLAGS entry");
goto exit_errmsg;
}
if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
@ -2624,7 +2834,7 @@ static void load_elf_image(const char *image_name, int image_fd,
retval = pread(image_fd, &abiflags, sizeof(Mips_elf_abiflags_v0),
eppnt->p_offset);
if (retval != sizeof(Mips_elf_abiflags_v0)) {
goto exit_perror;
goto exit_read;
}
}
bswap_mips_abiflags(&abiflags);
@ -2649,13 +2859,16 @@ static void load_elf_image(const char *image_name, int image_fd,
exit_read:
if (retval >= 0) {
errmsg = "Incomplete read of file header";
goto exit_errmsg;
error_setg(&err, "Incomplete read of file header");
} else {
error_setg_errno(&err, errno, "Error reading file header");
}
exit_perror:
errmsg = strerror(errno);
goto exit_errmsg;
exit_mmap:
error_setg_errno(&err, errno, "Error mapping file");
goto exit_errmsg;
exit_errmsg:
fprintf(stderr, "%s: %s\n", image_name, errmsg);
error_reportf_err(err, "%s: ", image_name);
exit(-1);
}
@ -2663,26 +2876,27 @@ static void load_elf_interp(const char *filename, struct image_info *info,
char bprm_buf[BPRM_BUF_SIZE])
{
int fd, retval;
Error *err = NULL;
fd = open(path(filename), O_RDONLY);
if (fd < 0) {
goto exit_perror;
error_setg_file_open(&err, errno, filename);
error_report_err(err);
exit(-1);
}
retval = read(fd, bprm_buf, BPRM_BUF_SIZE);
if (retval < 0) {
goto exit_perror;
error_setg_errno(&err, errno, "Error reading file header");
error_reportf_err(err, "%s: ", filename);
exit(-1);
}
if (retval < BPRM_BUF_SIZE) {
memset(bprm_buf + retval, 0, BPRM_BUF_SIZE - retval);
}
load_elf_image(filename, fd, info, NULL, bprm_buf);
return;
exit_perror:
fprintf(stderr, "%s: %s\n", filename, strerror(errno));
exit(-1);
}
static int symfind(const void *s0, const void *s1)
@ -2961,7 +3175,7 @@ int load_elf_binary(struct linux_binprm *bprm, struct image_info *info)
if (elf_interpreter) {
info->load_bias = interp_info.load_bias;
info->entry = interp_info.entry;
free(elf_interpreter);
g_free(elf_interpreter);
}
#ifdef USE_ELF_CORE_DUMP

16
linux-user/mmap.c
View File

@ -83,6 +83,22 @@ static int validate_prot_to_pageflags(int *host_prot, int prot)
*host_prot = (prot & (PROT_READ | PROT_WRITE))
| (prot & PROT_EXEC ? PROT_READ : 0);
#ifdef TARGET_AARCH64
/*
* The PROT_BTI bit is only accepted if the cpu supports the feature.
* Since this is the unusual case, don't bother checking unless
* the bit has been requested. If set and valid, record the bit
* within QEMU's page_flags.
*/
if (prot & TARGET_PROT_BTI) {
ARMCPU *cpu = ARM_CPU(thread_cpu);
if (cpu_isar_feature(aa64_bti, cpu)) {
valid |= TARGET_PROT_BTI;
page_flags |= PAGE_BTI;
}
}
#endif
return prot & ~valid ? 0 : page_flags;
}

4
linux-user/qemu.h
View File

@ -61,6 +61,10 @@ struct image_info {
abi_ulong interpreter_loadmap_addr;
abi_ulong interpreter_pt_dynamic_addr;
struct image_info *other_info;
/* For target-specific processing of NT_GNU_PROPERTY_TYPE_0. */
uint32_t note_flags;
#ifdef TARGET_MIPS
int fp_abi;
int interp_fp_abi;

4
linux-user/syscall_defs.h
View File

@ -1277,6 +1277,10 @@ struct target_winsize {
#define TARGET_PROT_SEM 0x08
#endif
#ifdef TARGET_AARCH64
#define TARGET_PROT_BTI 0x10
#endif
/* Common */
#define TARGET_MAP_SHARED 0x01 /* Share changes */
#define TARGET_MAP_PRIVATE 0x02 /* Changes are private */

5
target/arm/cpu.h
View File

@ -3445,6 +3445,11 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
/*
* AArch64 usage of the PAGE_TARGET_* bits for linux-user.
*/
#define PAGE_BTI PAGE_TARGET_1
/*
* Naming convention for isar_feature functions:
* Functions which test 32-bit ID registers should have _aa32_ in

6
target/arm/translate-a64.c
View File

@ -14507,10 +14507,10 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
*/
static bool is_guarded_page(CPUARMState *env, DisasContext *s)
{
#ifdef CONFIG_USER_ONLY
return false; /* FIXME */
#else
uint64_t addr = s->base.pc_first;
#ifdef CONFIG_USER_ONLY
return page_get_flags(addr) & PAGE_BTI;
#else
int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx);
unsigned int index = tlb_index(env, mmu_idx, addr);
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);

6
tests/qtest/meson.build
View File

@ -133,7 +133,11 @@ qtests_sparc64 = \
(config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \
['prom-env-test', 'boot-serial-test']
qtests_npcm7xx = ['npcm7xx_timer-test']
qtests_npcm7xx = \
['npcm7xx_gpio-test',
'npcm7xx_rng-test',
'npcm7xx_timer-test',
'npcm7xx_watchdog_timer-test']
qtests_arm = \
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \

385
tests/qtest/npcm7xx_gpio-test.c Normal file
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@ -0,0 +1,385 @@
/*
* QTest testcase for the Nuvoton NPCM7xx GPIO modules.
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include "qemu/osdep.h"
#include "libqtest-single.h"
#define NR_GPIO_DEVICES (8)
#define GPIO(x) (0xf0010000 + (x) * 0x1000)
#define GPIO_IRQ(x) (116 + (x))
/* GPIO registers */
#define GP_N_TLOCK1 0x00
#define GP_N_DIN 0x04 /* Data IN */
#define GP_N_POL 0x08 /* Polarity */
#define GP_N_DOUT 0x0c /* Data OUT */
#define GP_N_OE 0x10 /* Output Enable */
#define GP_N_OTYP 0x14
#define GP_N_MP 0x18
#define GP_N_PU 0x1c /* Pull-up */
#define GP_N_PD 0x20 /* Pull-down */
#define GP_N_DBNC 0x24 /* Debounce */
#define GP_N_EVTYP 0x28 /* Event Type */
#define GP_N_EVBE 0x2c /* Event Both Edge */
#define GP_N_OBL0 0x30
#define GP_N_OBL1 0x34
#define GP_N_OBL2 0x38
#define GP_N_OBL3 0x3c
#define GP_N_EVEN 0x40 /* Event Enable */
#define GP_N_EVENS 0x44 /* Event Set (enable) */
#define GP_N_EVENC 0x48 /* Event Clear (disable) */
#define GP_N_EVST 0x4c /* Event Status */
#define GP_N_SPLCK 0x50
#define GP_N_MPLCK 0x54
#define GP_N_IEM 0x58 /* Input Enable */
#define GP_N_OSRC 0x5c
#define GP_N_ODSC 0x60
#define GP_N_DOS 0x68 /* Data OUT Set */
#define GP_N_DOC 0x6c /* Data OUT Clear */
#define GP_N_OES 0x70 /* Output Enable Set */
#define GP_N_OEC 0x74 /* Output Enable Clear */
#define GP_N_TLOCK2 0x7c
static void gpio_unlock(int n)
{
if (readl(GPIO(n) + GP_N_TLOCK1) != 0) {
writel(GPIO(n) + GP_N_TLOCK2, 0xc0de1248);
writel(GPIO(n) + GP_N_TLOCK1, 0xc0defa73);
}
}
/* Restore the GPIO controller to a sensible default state. */
static void gpio_reset(int n)
{
gpio_unlock(0);
writel(GPIO(n) + GP_N_EVEN, 0x00000000);
writel(GPIO(n) + GP_N_EVST, 0xffffffff);
writel(GPIO(n) + GP_N_POL, 0x00000000);
writel(GPIO(n) + GP_N_DOUT, 0x00000000);
writel(GPIO(n) + GP_N_OE, 0x00000000);
writel(GPIO(n) + GP_N_OTYP, 0x00000000);
writel(GPIO(n) + GP_N_PU, 0xffffffff);
writel(GPIO(n) + GP_N_PD, 0x00000000);
writel(GPIO(n) + GP_N_IEM, 0xffffffff);
}
static void test_dout_to_din(void)
{
gpio_reset(0);
/* When output is enabled, DOUT should be reflected on DIN. */
writel(GPIO(0) + GP_N_OE, 0xffffffff);
/* PU and PD shouldn't have any impact on DIN. */
writel(GPIO(0) + GP_N_PU, 0xffff0000);
writel(GPIO(0) + GP_N_PD, 0x0000ffff);
writel(GPIO(0) + GP_N_DOUT, 0x12345678);
g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x12345678);
g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x12345678);
}
static void test_pullup_pulldown(void)
{
gpio_reset(0);
/*
* When output is disabled, and PD is the inverse of PU, PU should be
* reflected on DIN. If PD is not the inverse of PU, the state of DIN is
* undefined, so we don't test that.
*/
writel(GPIO(0) + GP_N_OE, 0x00000000);
/* DOUT shouldn't have any impact on DIN. */
writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
writel(GPIO(0) + GP_N_PU, 0x23456789);
writel(GPIO(0) + GP_N_PD, ~0x23456789U);
g_assert_cmphex(readl(GPIO(0) + GP_N_PU), ==, 0x23456789);
g_assert_cmphex(readl(GPIO(0) + GP_N_PD), ==, ~0x23456789U);
g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x23456789);
}
static void test_output_enable(void)
{
gpio_reset(0);
/*
* With all pins weakly pulled down, and DOUT all-ones, OE should be
* reflected on DIN.
*/
writel(GPIO(0) + GP_N_DOUT, 0xffffffff);
writel(GPIO(0) + GP_N_PU, 0x00000000);
writel(GPIO(0) + GP_N_PD, 0xffffffff);
writel(GPIO(0) + GP_N_OE, 0x3456789a);
g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3456789a);
g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3456789a);
writel(GPIO(0) + GP_N_OEC, 0x00030002);
g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x34547898);
g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x34547898);
writel(GPIO(0) + GP_N_OES, 0x0000f001);
g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3454f899);
g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3454f899);
}
static void test_open_drain(void)
{
gpio_reset(0);
/*
* Upper half of DOUT drives a 1 only if the corresponding bit in OTYP is
* not set. If OTYP is set, DIN is determined by PU/PD. Lower half of
* DOUT always drives a 0 regardless of OTYP; PU/PD have no effect. When
* OE is 0, output is determined by PU/PD; OTYP has no effect.
*/
writel(GPIO(0) + GP_N_OTYP, 0x456789ab);
writel(GPIO(0) + GP_N_OE, 0xf0f0f0f0);
writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
writel(GPIO(0) + GP_N_PU, 0xff00ff00);
writel(GPIO(0) + GP_N_PD, 0x00ff00ff);
g_assert_cmphex(readl(GPIO(0) + GP_N_OTYP), ==, 0x456789ab);
g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff900f00);
}
static void test_polarity(void)
{
gpio_reset(0);
/*
* In push-pull mode, DIN should reflect DOUT because the signal is
* inverted in both directions.
*/
writel(GPIO(0) + GP_N_OTYP, 0x00000000);
writel(GPIO(0) + GP_N_OE, 0xffffffff);
writel(GPIO(0) + GP_N_DOUT, 0x56789abc);
writel(GPIO(0) + GP_N_POL, 0x6789abcd);
g_assert_cmphex(readl(GPIO(0) + GP_N_POL), ==, 0x6789abcd);
g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x56789abc);
/*
* When turning off the drivers, DIN should reflect the inverse of the
* pulled-up lines.
*/
writel(GPIO(0) + GP_N_OE, 0x00000000);
writel(GPIO(0) + GP_N_POL, 0xffffffff);
writel(GPIO(0) + GP_N_PU, 0x789abcde);
writel(GPIO(0) + GP_N_PD, ~0x789abcdeU);
g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, ~0x789abcdeU);
/*
* In open-drain mode, DOUT=1 will appear to drive the pin high (since DIN
* is inverted), while DOUT=0 will leave the pin floating.
*/
writel(GPIO(0) + GP_N_OTYP, 0xffffffff);
writel(GPIO(0) + GP_N_OE, 0xffffffff);
writel(GPIO(0) + GP_N_PU, 0xffff0000);
writel(GPIO(0) + GP_N_PD, 0x0000ffff);
writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff00ffff);
}
static void test_input_mask(void)
{
gpio_reset(0);
/* IEM=0 forces the input to zero before polarity inversion. */
writel(GPIO(0) + GP_N_OE, 0xffffffff);
writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
writel(GPIO(0) + GP_N_POL, 0xffff0000);
writel(GPIO(0) + GP_N_IEM, 0x87654321);
g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff9a4300);
}
static void test_temp_lock(void)
{
gpio_reset(0);
writel(GPIO(0) + GP_N_DOUT, 0x98765432);
/* Make sure we're unlocked initially. */
g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);
/* Writing any value to TLOCK1 will lock. */
writel(GPIO(0) + GP_N_TLOCK1, 0);
g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 1);
writel(GPIO(0) + GP_N_DOUT, 0xa9876543);
g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x98765432);
/* Now, try to unlock. */
gpio_unlock(0);
g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);
writel(GPIO(0) + GP_N_DOUT, 0xa9876543);
g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0xa9876543);
/* Try it again, but write TLOCK2 to lock. */
writel(GPIO(0) + GP_N_TLOCK2, 0);
g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 1);
writel(GPIO(0) + GP_N_DOUT, 0x98765432);
g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0xa9876543);
/* Now, try to unlock. */
gpio_unlock(0);
g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);
writel(GPIO(0) + GP_N_DOUT, 0x98765432);
g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x98765432);
}
static void test_events_level(void)
{
gpio_reset(0);
writel(GPIO(0) + GP_N_EVTYP, 0x00000000);
writel(GPIO(0) + GP_N_DOUT, 0xba987654);
writel(GPIO(0) + GP_N_OE, 0xffffffff);
writel(GPIO(0) + GP_N_EVST, 0xffffffff);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba987654);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_DOUT, 0x00000000);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba987654);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_EVST, 0x00007654);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba980000);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_EVST, 0xba980000);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
}
static void test_events_rising_edge(void)
{
gpio_reset(0);
writel(GPIO(0) + GP_N_EVTYP, 0xffffffff);
writel(GPIO(0) + GP_N_EVBE, 0x00000000);
writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
writel(GPIO(0) + GP_N_OE, 0xffffffff);
writel(GPIO(0) + GP_N_EVST, 0xffffffff);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x0000ff00);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_DOUT, 0x00ff0000);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ffff00);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_EVST, 0x0000f000);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ff0f00);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_EVST, 0x00ff0f00);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
}
static void test_events_both_edges(void)
{
gpio_reset(0);
writel(GPIO(0) + GP_N_EVTYP, 0xffffffff);
writel(GPIO(0) + GP_N_EVBE, 0xffffffff);
writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
writel(GPIO(0) + GP_N_OE, 0xffffffff);
writel(GPIO(0) + GP_N_EVST, 0xffffffff);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ffff00);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_DOUT, 0xef00ff08);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x10ffff08);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_EVST, 0x0000f000);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x10ff0f08);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
writel(GPIO(0) + GP_N_EVST, 0x10ff0f08);
g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
}
static void test_gpion_irq(gconstpointer test_data)
{
intptr_t n = (intptr_t)test_data;
gpio_reset(n);
writel(GPIO(n) + GP_N_EVTYP, 0x00000000);
writel(GPIO(n) + GP_N_DOUT, 0x00000000);
writel(GPIO(n) + GP_N_OE, 0xffffffff);
writel(GPIO(n) + GP_N_EVST, 0xffffffff);
writel(GPIO(n) + GP_N_EVEN, 0x00000000);
/* Trigger an event; interrupts are masked. */
g_assert_cmphex(readl(GPIO(n) + GP_N_EVST), ==, 0x00000000);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
writel(GPIO(n) + GP_N_DOS, 0x00008000);
g_assert_cmphex(readl(GPIO(n) + GP_N_EVST), ==, 0x00008000);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
/* Unmask all event interrupts; verify that the interrupt fired. */
writel(GPIO(n) + GP_N_EVEN, 0xffffffff);
g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
/* Clear the current bit, set a new bit, irq stays asserted. */
writel(GPIO(n) + GP_N_DOC, 0x00008000);
g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
writel(GPIO(n) + GP_N_DOS, 0x00000200);
g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
writel(GPIO(n) + GP_N_EVST, 0x00008000);
g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
/* Mask/unmask the event that's currently active. */
writel(GPIO(n) + GP_N_EVENC, 0x00000200);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
writel(GPIO(n) + GP_N_EVENS, 0x00000200);
g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
/* Clear the input and the status bit, irq is deasserted. */
writel(GPIO(n) + GP_N_DOC, 0x00000200);
g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
writel(GPIO(n) + GP_N_EVST, 0x00000200);
g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
}
int main(int argc, char **argv)
{
int ret;
int i;
g_test_init(&argc, &argv, NULL);
g_test_set_nonfatal_assertions();
qtest_add_func("/npcm7xx_gpio/dout_to_din", test_dout_to_din);
qtest_add_func("/npcm7xx_gpio/pullup_pulldown", test_pullup_pulldown);
qtest_add_func("/npcm7xx_gpio/output_enable", test_output_enable);
qtest_add_func("/npcm7xx_gpio/open_drain", test_open_drain);
qtest_add_func("/npcm7xx_gpio/polarity", test_polarity);
qtest_add_func("/npcm7xx_gpio/input_mask", test_input_mask);
qtest_add_func("/npcm7xx_gpio/temp_lock", test_temp_lock);
qtest_add_func("/npcm7xx_gpio/events/level", test_events_level);
qtest_add_func("/npcm7xx_gpio/events/rising_edge", test_events_rising_edge);
qtest_add_func("/npcm7xx_gpio/events/both_edges", test_events_both_edges);
for (i = 0; i < NR_GPIO_DEVICES; i++) {
g_autofree char *test_name =
g_strdup_printf("/npcm7xx_gpio/gpio[%d]/irq", i);
qtest_add_data_func(test_name, (void *)(intptr_t)i, test_gpion_irq);
}
qtest_start("-machine npcm750-evb");
qtest_irq_intercept_in(global_qtest, "/machine/soc/a9mpcore/gic");
ret = g_test_run();
qtest_end();
return ret;
}

278
tests/qtest/npcm7xx_rng-test.c Normal file
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@ -0,0 +1,278 @@
/*
* QTest testcase for the Nuvoton NPCM7xx Random Number Generator
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include "qemu/osdep.h"
#include <math.h>
#include "libqtest-single.h"
#include "qemu/bitops.h"
#define RNG_BASE_ADDR 0xf000b000
/* Control and Status Register */
#define RNGCS 0x00
# define DVALID BIT(1) /* Data Valid */
# define RNGE BIT(0) /* RNG Enable */
/* Data Register */
#define RNGD 0x04
/* Mode Register */
#define RNGMODE 0x08
# define ROSEL_NORMAL (2) /* RNG only works in this mode */
/* Number of bits to collect for randomness tests. */
#define TEST_INPUT_BITS (128)
static void rng_writeb(unsigned int offset, uint8_t value)
{
writeb(RNG_BASE_ADDR + offset, value);
}
static uint8_t rng_readb(unsigned int offset)
{
return readb(RNG_BASE_ADDR + offset);
}
/* Disable RNG and set normal ring oscillator mode. */
static void rng_reset(void)
{
rng_writeb(RNGCS, 0);
rng_writeb(RNGMODE, ROSEL_NORMAL);
}
/* Reset RNG and then enable it. */
static void rng_reset_enable(void)
{
rng_reset();
rng_writeb(RNGCS, RNGE);
}
/* Wait until Data Valid bit is set. */
static bool rng_wait_ready(void)
{
/* qemu_guest_getrandom may fail. Assume it won't fail 10 times in a row. */
int retries = 10;
while (retries-- > 0) {
if (rng_readb(RNGCS) & DVALID) {
return true;
}
}
return false;
}
/*
* Perform a frequency (monobit) test, as defined by NIST SP 800-22, on the
* sequence in buf and return the P-value. This represents the probability of a
* truly random sequence having the same proportion of zeros and ones as the
* sequence in buf.
*
* An RNG which always returns 0x00 or 0xff, or has some bits stuck at 0 or 1,
* will fail this test. However, an RNG which always returns 0x55, 0xf0 or some
* other value with an equal number of zeroes and ones will pass.
*/
static double calc_monobit_p(const uint8_t *buf, unsigned int len)
{
unsigned int i;
double s_obs;
int sn = 0;
for (i = 0; i < len; i++) {
/*
* Each 1 counts as 1, each 0 counts as -1.
* s = cp - (8 - cp) = 2 * cp - 8
*/
sn += 2 * ctpop8(buf[i]) - 8;
}
s_obs = abs(sn) / sqrt(len * BITS_PER_BYTE);
return erfc(s_obs / sqrt(2));
}
/*
* Perform a runs test, as defined by NIST SP 800-22, and return the P-value.
* This represents the probability of a truly random sequence having the same
* number of runs (i.e. uninterrupted sequences of identical bits) as the
* sequence in buf.
*/
static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
{
unsigned int j;
unsigned int k;
int nr_ones = 0;
int vn_obs = 0;
double pi;
g_assert(nr_bits % BITS_PER_LONG == 0);
for (j = 0; j < nr_bits / BITS_PER_LONG; j++) {
nr_ones += __builtin_popcountl(buf[j]);
}
pi = (double)nr_ones / nr_bits;
for (k = 0; k < nr_bits - 1; k++) {
vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
}
vn_obs += 1;
return erfc(fabs(vn_obs - 2 * nr_bits * pi * (1.0 - pi))
/ (2 * sqrt(2 * nr_bits) * pi * (1.0 - pi)));
}
/*
* Verifies that DVALID is clear, and RNGD reads zero, when RNGE is cleared,
* and DVALID eventually becomes set when RNGE is set.
*/
static void test_enable_disable(void)
{
/* Disable: DVALID should not be set, and RNGD should read zero */
rng_reset();
g_assert_cmphex(rng_readb(RNGCS), ==, 0);
g_assert_cmphex(rng_readb(RNGD), ==, 0);
/* Enable: DVALID should be set, but we can't make assumptions about RNGD */
rng_writeb(RNGCS, RNGE);
g_assert_true(rng_wait_ready());
g_assert_cmphex(rng_readb(RNGCS), ==, DVALID | RNGE);
/* Disable: DVALID should not be set, and RNGD should read zero */
rng_writeb(RNGCS, 0);
g_assert_cmphex(rng_readb(RNGCS), ==, 0);
g_assert_cmphex(rng_readb(RNGD), ==, 0);
}
/*
* Verifies that the RNG only produces data when RNGMODE is set to 'normal'
* ring oscillator mode.
*/
static void test_rosel(void)
{
rng_reset_enable();
g_assert_true(rng_wait_ready());
rng_writeb(RNGMODE, 0);
g_assert_false(rng_wait_ready());
rng_writeb(RNGMODE, ROSEL_NORMAL);
g_assert_true(rng_wait_ready());
rng_writeb(RNGMODE, 0);
g_assert_false(rng_wait_ready());
}
/*
* Verifies that a continuous sequence of bits collected after enabling the RNG
* satisfies a monobit test.
*/
static void test_continuous_monobit(void)
{
uint8_t buf[TEST_INPUT_BITS / BITS_PER_BYTE];
unsigned int i;
rng_reset_enable();
for (i = 0; i < sizeof(buf); i++) {
g_assert_true(rng_wait_ready());
buf[i] = rng_readb(RNGD);
}
g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
}
/*
* Verifies that a continuous sequence of bits collected after enabling the RNG
* satisfies a runs test.
*/
static void test_continuous_runs(void)
{
union {
unsigned long l[TEST_INPUT_BITS / BITS_PER_LONG];
uint8_t c[TEST_INPUT_BITS / BITS_PER_BYTE];
} buf;
unsigned int i;
rng_reset_enable();
for (i = 0; i < sizeof(buf); i++) {
g_assert_true(rng_wait_ready());
buf.c[i] = rng_readb(RNGD);
}
g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
}
/*
* Verifies that the first data byte collected after enabling the RNG satisfies
* a monobit test.
*/
static void test_first_byte_monobit(void)
{
/* Enable, collect one byte, disable. Repeat until we have 100 bits. */
uint8_t buf[TEST_INPUT_BITS / BITS_PER_BYTE];
unsigned int i;
rng_reset();
for (i = 0; i < sizeof(buf); i++) {
rng_writeb(RNGCS, RNGE);
g_assert_true(rng_wait_ready());
buf[i] = rng_readb(RNGD);
rng_writeb(RNGCS, 0);
}
g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
}
/*
* Verifies that the first data byte collected after enabling the RNG satisfies
* a runs test.
*/
static void test_first_byte_runs(void)
{
/* Enable, collect one byte, disable. Repeat until we have 100 bits. */
union {
unsigned long l[TEST_INPUT_BITS / BITS_PER_LONG];
uint8_t c[TEST_INPUT_BITS / BITS_PER_BYTE];
} buf;
unsigned int i;
rng_reset();
for (i = 0; i < sizeof(buf); i++) {
rng_writeb(RNGCS, RNGE);
g_assert_true(rng_wait_ready());
buf.c[i] = rng_readb(RNGD);
rng_writeb(RNGCS, 0);
}
g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
}
int main(int argc, char **argv)
{
int ret;
g_test_init(&argc, &argv, NULL);
g_test_set_nonfatal_assertions();
qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable);
qtest_add_func("npcm7xx_rng/rosel", test_rosel);
qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
qtest_start("-machine npcm750-evb");
ret = g_test_run();
qtest_end();
return ret;
}

319
tests/qtest/npcm7xx_watchdog_timer-test.c Normal file
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@ -0,0 +1,319 @@
/*
* QTests for Nuvoton NPCM7xx Timer Watchdog Modules.
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include "qemu/osdep.h"
#include "qemu/timer.h"
#include "libqos/libqtest.h"
#include "qapi/qmp/qdict.h"
#define WTCR_OFFSET 0x1c
#define REF_HZ (25000000)
/* WTCR bit fields */
#define WTCLK(rv) ((rv) << 10)
#define WTE BIT(7)
#define WTIE BIT(6)
#define WTIS(rv) ((rv) << 4)
#define WTIF BIT(3)
#define WTRF BIT(2)
#define WTRE BIT(1)
#define WTR BIT(0)
typedef struct Watchdog {
int irq;
uint64_t base_addr;
} Watchdog;
static const Watchdog watchdog_list[] = {
{
.irq = 47,
.base_addr = 0xf0008000
},
{
.irq = 48,
.base_addr = 0xf0009000
},
{
.irq = 49,
.base_addr = 0xf000a000
}
};
static int watchdog_index(const Watchdog *wd)
{
ptrdiff_t diff = wd - watchdog_list;
g_assert(diff >= 0 && diff < ARRAY_SIZE(watchdog_list));
return diff;
}
static uint32_t watchdog_read_wtcr(QTestState *qts, const Watchdog *wd)
{
return qtest_readl(qts, wd->base_addr + WTCR_OFFSET);
}
static void watchdog_write_wtcr(QTestState *qts, const Watchdog *wd,
uint32_t value)
{
qtest_writel(qts, wd->base_addr + WTCR_OFFSET, value);
}
static uint32_t watchdog_prescaler(QTestState *qts, const Watchdog *wd)
{
switch (extract32(watchdog_read_wtcr(qts, wd), 10, 2)) {
case 0:
return 1;
case 1:
return 256;
case 2:
return 2048;
case 3:
return 65536;
default:
g_assert_not_reached();
}
}
static QDict *get_watchdog_action(QTestState *qts)
{
QDict *ev = qtest_qmp_eventwait_ref(qts, "WATCHDOG");
QDict *data;
data = qdict_get_qdict(ev, "data");
qobject_ref(data);
qobject_unref(ev);
return data;
}
#define RESET_CYCLES 1024
static uint32_t watchdog_interrupt_cycles(QTestState *qts, const Watchdog *wd)
{
uint32_t wtis = extract32(watchdog_read_wtcr(qts, wd), 4, 2);
return 1 << (14 + 2 * wtis);
}
static int64_t watchdog_calculate_steps(uint32_t count, uint32_t prescale)
{
return (NANOSECONDS_PER_SECOND / REF_HZ) * count * prescale;
}
static int64_t watchdog_interrupt_steps(QTestState *qts, const Watchdog *wd)
{
return watchdog_calculate_steps(watchdog_interrupt_cycles(qts, wd),
watchdog_prescaler(qts, wd));
}
/* Check wtcr can be reset to default value */
static void test_init(gconstpointer watchdog)
{
const Watchdog *wd = watchdog;
QTestState *qts = qtest_init("-machine quanta-gsj");
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
watchdog_write_wtcr(qts, wd, WTCLK(1) | WTRF | WTIF | WTR);
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(1));
qtest_quit(qts);
}
/* Check a watchdog can generate interrupt and reset actions */
static void test_reset_action(gconstpointer watchdog)
{
const Watchdog *wd = watchdog;
QTestState *qts = qtest_init("-machine quanta-gsj");
QDict *ad;
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
watchdog_write_wtcr(qts, wd,
WTCLK(0) | WTE | WTRF | WTRE | WTIF | WTIE | WTR);
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
WTCLK(0) | WTE | WTRE | WTIE);
/* Check a watchdog can generate an interrupt */
qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
WTCLK(0) | WTE | WTIF | WTIE | WTRE);
g_assert_true(qtest_get_irq(qts, wd->irq));
/* Check a watchdog can generate a reset signal */
qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
watchdog_prescaler(qts, wd)));
ad = get_watchdog_action(qts);
/* The signal is a reset signal */
g_assert_false(strcmp(qdict_get_str(ad, "action"), "reset"));
qobject_unref(ad);
qtest_qmp_eventwait(qts, "RESET");
/*
* Make sure WTCR is reset to default except for WTRF bit which shouldn't
* be reset.
*/
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(1) | WTRF);
qtest_quit(qts);
}
/* Check a watchdog works with all possible WTCLK prescalers and WTIS cycles */
static void test_prescaler(gconstpointer watchdog)
{
const Watchdog *wd = watchdog;
for (int wtclk = 0; wtclk < 4; ++wtclk) {
for (int wtis = 0; wtis < 4; ++wtis) {
QTestState *qts = qtest_init("-machine quanta-gsj");
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
watchdog_write_wtcr(qts, wd,
WTCLK(wtclk) | WTE | WTIF | WTIS(wtis) | WTIE | WTR);
/*
* The interrupt doesn't fire until watchdog_interrupt_steps()
* cycles passed
*/
qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd) - 1);
g_assert_false(watchdog_read_wtcr(qts, wd) & WTIF);
g_assert_false(qtest_get_irq(qts, wd->irq));
qtest_clock_step(qts, 1);
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
g_assert_true(qtest_get_irq(qts, wd->irq));
qtest_quit(qts);
}
}
}
/*
* Check a watchdog doesn't fire if corresponding flags (WTIE and WTRE) are not
* set.
*/
static void test_enabling_flags(gconstpointer watchdog)
{
const Watchdog *wd = watchdog;
QTestState *qts;
/* Neither WTIE or WTRE is set, no interrupt or reset should happen */
qts = qtest_init("-machine quanta-gsj");
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTRF | WTR);
qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
g_assert_false(qtest_get_irq(qts, wd->irq));
qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
watchdog_prescaler(qts, wd)));
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
g_assert_false(watchdog_read_wtcr(qts, wd) & WTRF);
qtest_quit(qts);
/* Only WTIE is set, interrupt is triggered but reset should not happen */
qts = qtest_init("-machine quanta-gsj");
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTIE | WTRF | WTR);
qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
g_assert_true(qtest_get_irq(qts, wd->irq));
qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
watchdog_prescaler(qts, wd)));
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
g_assert_false(watchdog_read_wtcr(qts, wd) & WTRF);
qtest_quit(qts);
/* Only WTRE is set, interrupt is triggered but reset should not happen */
qts = qtest_init("-machine quanta-gsj");
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTRE | WTRF | WTR);
qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
g_assert_false(qtest_get_irq(qts, wd->irq));
qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
watchdog_prescaler(qts, wd)));
g_assert_false(strcmp(qdict_get_str(get_watchdog_action(qts), "action"),
"reset"));
qtest_qmp_eventwait(qts, "RESET");
qtest_quit(qts);
/*
* The case when both flags are set is already tested in
* test_reset_action().
*/
}
/* Check a watchdog can pause and resume by setting WTE bits */
static void test_pause(gconstpointer watchdog)
{
const Watchdog *wd = watchdog;
QTestState *qts;
int64_t remaining_steps, steps;
qts = qtest_init("-machine quanta-gsj");
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTIE | WTRF | WTR);
remaining_steps = watchdog_interrupt_steps(qts, wd);
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTE | WTIE);
/* Run for half of the execution period. */
steps = remaining_steps / 2;
remaining_steps -= steps;
qtest_clock_step(qts, steps);
/* Pause the watchdog */
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTIE);
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTIE);
/* Run for a long period of time, the watchdog shouldn't fire */
qtest_clock_step(qts, steps << 4);
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTIE);
g_assert_false(qtest_get_irq(qts, wd->irq));
/* Resume the watchdog */
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIE);
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTE | WTIE);
/* Run for the reset of the execution period, the watchdog should fire */
qtest_clock_step(qts, remaining_steps);
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
WTCLK(0) | WTE | WTIF | WTIE);
g_assert_true(qtest_get_irq(qts, wd->irq));
qtest_quit(qts);
}
static void watchdog_add_test(const char *name, const Watchdog* wd,
GTestDataFunc fn)
{
g_autofree char *full_name = g_strdup_printf(
"npcm7xx_watchdog_timer[%d]/%s", watchdog_index(wd), name);
qtest_add_data_func(full_name, wd, fn);
}
#define add_test(name, td) watchdog_add_test(#name, td, test_##name)
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
g_test_set_nonfatal_assertions();
for (int i = 0; i < ARRAY_SIZE(watchdog_list); ++i) {
const Watchdog *wd = &watchdog_list[i];
add_test(init, wd);
add_test(reset_action, wd);
add_test(prescaler, wd);
add_test(enabling_flags, wd);
add_test(pause, wd);
}
return g_test_run();
}

10
tests/tcg/aarch64/Makefile.target
View File

@ -25,6 +25,16 @@ run-pauth-%: QEMU_OPTS += -cpu max
run-plugin-pauth-%: QEMU_OPTS += -cpu max
endif
# BTI Tests
# bti-1 tests the elf notes, so we require special compiler support.
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_BTI),)
AARCH64_TESTS += bti-1
bti-1: CFLAGS += -mbranch-protection=standard
bti-1: LDFLAGS += -nostdlib
endif
# bti-2 tests PROT_BTI, so no special compiler support required.
AARCH64_TESTS += bti-2
# Semihosting smoke test for linux-user
AARCH64_TESTS += semihosting
run-semihosting: semihosting

62
tests/tcg/aarch64/bti-1.c Normal file
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@ -0,0 +1,62 @@
/*
* Branch target identification, basic notskip cases.
*/
#include "bti-crt.inc.c"
static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
{
uc->uc_mcontext.pc += 8;
uc->uc_mcontext.pstate = 1;
}
#define NOP "nop"
#define BTI_N "hint #32"
#define BTI_C "hint #34"
#define BTI_J "hint #36"
#define BTI_JC "hint #38"
#define BTYPE_1(DEST) \
asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \
: "=r"(skipped) : : "x16")
#define BTYPE_2(DEST) \
asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \
: "=r"(skipped) : : "x16", "x30")
#define BTYPE_3(DEST) \
asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \
: "=r"(skipped) : : "x15")
#define TEST(WHICH, DEST, EXPECT) \
do { WHICH(DEST); fail += skipped ^ EXPECT; } while (0)
int main()
{
int fail = 0;
int skipped;
/* Signal-like with SA_SIGINFO. */
signal_info(SIGILL, skip2_sigill);
TEST(BTYPE_1, NOP, 1);
TEST(BTYPE_1, BTI_N, 1);
TEST(BTYPE_1, BTI_C, 0);
TEST(BTYPE_1, BTI_J, 0);
TEST(BTYPE_1, BTI_JC, 0);
TEST(BTYPE_2, NOP, 1);
TEST(BTYPE_2, BTI_N, 1);
TEST(BTYPE_2, BTI_C, 0);
TEST(BTYPE_2, BTI_J, 1);
TEST(BTYPE_2, BTI_JC, 0);
TEST(BTYPE_3, NOP, 1);
TEST(BTYPE_3, BTI_N, 1);
TEST(BTYPE_3, BTI_C, 1);
TEST(BTYPE_3, BTI_J, 0);
TEST(BTYPE_3, BTI_JC, 0);
return fail;
}

116
tests/tcg/aarch64/bti-2.c Normal file
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@ -0,0 +1,116 @@
/*
* Branch target identification, basic notskip cases.
*/
#include <stdio.h>
#include <signal.h>
#include <string.h>
#include <unistd.h>
#include <sys/mman.h>
#ifndef PROT_BTI
#define PROT_BTI 0x10
#endif
static void skip2_sigill(int sig, siginfo_t *info, void *vuc)
{
ucontext_t *uc = vuc;
uc->uc_mcontext.pc += 8;
uc->uc_mcontext.pstate = 1;
}
#define NOP "nop"
#define BTI_N "hint #32"
#define BTI_C "hint #34"
#define BTI_J "hint #36"
#define BTI_JC "hint #38"
#define BTYPE_1(DEST) \
"mov x1, #1\n\t" \
"adr x16, 1f\n\t" \
"br x16\n" \
"1: " DEST "\n\t" \
"mov x1, #0"
#define BTYPE_2(DEST) \
"mov x1, #1\n\t" \
"adr x16, 1f\n\t" \
"blr x16\n" \
"1: " DEST "\n\t" \
"mov x1, #0"
#define BTYPE_3(DEST) \
"mov x1, #1\n\t" \
"adr x15, 1f\n\t" \
"br x15\n" \
"1: " DEST "\n\t" \
"mov x1, #0"
#define TEST(WHICH, DEST, EXPECT) \
WHICH(DEST) "\n" \
".if " #EXPECT "\n\t" \
"eor x1, x1," #EXPECT "\n" \
".endif\n\t" \
"add x0, x0, x1\n\t"
asm("\n"
"test_begin:\n\t"
BTI_C "\n\t"
"mov x2, x30\n\t"
"mov x0, #0\n\t"
TEST(BTYPE_1, NOP, 1)
TEST(BTYPE_1, BTI_N, 1)
TEST(BTYPE_1, BTI_C, 0)
TEST(BTYPE_1, BTI_J, 0)
TEST(BTYPE_1, BTI_JC, 0)
TEST(BTYPE_2, NOP, 1)
TEST(BTYPE_2, BTI_N, 1)
TEST(BTYPE_2, BTI_C, 0)
TEST(BTYPE_2, BTI_J, 1)
TEST(BTYPE_2, BTI_JC, 0)
TEST(BTYPE_3, NOP, 1)
TEST(BTYPE_3, BTI_N, 1)
TEST(BTYPE_3, BTI_C, 1)
TEST(BTYPE_3, BTI_J, 0)
TEST(BTYPE_3, BTI_JC, 0)
"ret x2\n"
"test_end:"
);
int main()
{
struct sigaction sa;
void *tb, *te;
void *p = mmap(0, getpagesize(),
PROT_EXEC | PROT_READ | PROT_WRITE | PROT_BTI,
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
if (p == MAP_FAILED) {
perror("mmap");
return 1;
}
memset(&sa, 0, sizeof(sa));
sa.sa_sigaction = skip2_sigill;
sa.sa_flags = SA_SIGINFO;
if (sigaction(SIGILL, &sa, NULL) < 0) {
perror("sigaction");
return 1;
}
/*
* ??? With "extern char test_begin[]", some compiler versions
* will use :got references, and some linker versions will
* resolve this reference to a static symbol incorrectly.
* Bypass this error by using a pc-relative reference directly.
*/
asm("adr %0, test_begin; adr %1, test_end" : "=r"(tb), "=r"(te));
memcpy(p, tb, te - tb);
return ((int (*)(void))p)();
}

51
tests/tcg/aarch64/bti-crt.inc.c Normal file
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@ -0,0 +1,51 @@
/*
* Minimal user-environment for testing BTI.
*
* Normal libc is not (yet) built with BTI support enabled,
* and so could generate a BTI TRAP before ever reaching main.
*/
#include <stdlib.h>
#include <signal.h>
#include <ucontext.h>
#include <asm/unistd.h>
int main(void);
void _start(void)
{
exit(main());
}
void exit(int ret)
{
register int x0 __asm__("x0") = ret;
register int x8 __asm__("x8") = __NR_exit;
asm volatile("svc #0" : : "r"(x0), "r"(x8));
__builtin_unreachable();
}
/*
* Irritatingly, the user API struct sigaction does not match the
* kernel API struct sigaction. So for simplicity, isolate the
* kernel ABI here, and make this act like signal.
*/
void signal_info(int sig, void (*fn)(int, siginfo_t *, ucontext_t *))
{
struct kernel_sigaction {
void (*handler)(int, siginfo_t *, ucontext_t *);
unsigned long flags;
unsigned long restorer;
unsigned long mask;
} sa = { fn, SA_SIGINFO, 0, 0 };
register int x0 __asm__("x0") = sig;
register void *x1 __asm__("x1") = &sa;
register void *x2 __asm__("x2") = 0;
register int x3 __asm__("x3") = sizeof(unsigned long);
register int x8 __asm__("x8") = __NR_rt_sigaction;
asm volatile("svc #0"
: : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory");
}

4
tests/tcg/configure.sh
View File

@ -240,6 +240,10 @@ for target in $target_list; do
-march=armv8.3-a -o $TMPE $TMPC; then
echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
fi
if do_compiler "$target_compiler" $target_compiler_cflags \
-mbranch-protection=standard -o $TMPE $TMPC; then
echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
fi
;;
esac