mirror of https://github.com/proxmox/mirror_qemu
target/arm: Convert Logical (immediate) to decodetree
Convert the ADD, ORR, EOR, ANDS (immediate) instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-10-peter.maydell@linaro.org [PMM: rebased] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Richard Henderson
Peter Maydell
parent
000bcd008f
commit
8127f46a5b
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@ -56,3 +56,18 @@ SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12
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ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
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SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
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# Logical (immediate)
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&rri_log rd rn sf dbm
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@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1
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@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0
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AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64
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AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32
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ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64
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ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32
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EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64
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EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32
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ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64
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ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32
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@ -4288,7 +4288,12 @@ static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
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return mask;
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}
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/* Simplified variant of pseudocode DecodeBitMasks() for the case where we
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/*
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* Logical (immediate)
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*/
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/*
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* Simplified variant of pseudocode DecodeBitMasks() for the case where we
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* only require the wmask. Returns false if the imms/immr/immn are a reserved
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* value (ie should cause a guest UNDEF exception), and true if they are
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* valid, in which case the decoded bit pattern is written to result.
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@ -4354,78 +4359,40 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
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return true;
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}
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/* Logical (immediate)
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* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
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* +----+-----+-------------+---+------+------+------+------+
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* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
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* +----+-----+-------------+---+------+------+------+------+
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*/
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static void disas_logic_imm(DisasContext *s, uint32_t insn)
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static bool gen_rri_log(DisasContext *s, arg_rri_log *a, bool set_cc,
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void (*fn)(TCGv_i64, TCGv_i64, int64_t))
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{
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unsigned int sf, opc, is_n, immr, imms, rn, rd;
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TCGv_i64 tcg_rd, tcg_rn;
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uint64_t wmask;
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bool is_and = false;
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uint64_t imm;
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sf = extract32(insn, 31, 1);
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opc = extract32(insn, 29, 2);
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is_n = extract32(insn, 22, 1);
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immr = extract32(insn, 16, 6);
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imms = extract32(insn, 10, 6);
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rn = extract32(insn, 5, 5);
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rd = extract32(insn, 0, 5);
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if (!sf && is_n) {
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unallocated_encoding(s);
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return;
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/* Some immediate field values are reserved. */
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if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1),
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extract32(a->dbm, 0, 6),
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extract32(a->dbm, 6, 6))) {
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return false;
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}
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if (!a->sf) {
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imm &= 0xffffffffull;
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}
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if (opc == 0x3) { /* ANDS */
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tcg_rd = cpu_reg(s, rd);
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} else {
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tcg_rd = cpu_reg_sp(s, rd);
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}
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tcg_rn = cpu_reg(s, rn);
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tcg_rd = set_cc ? cpu_reg(s, a->rd) : cpu_reg_sp(s, a->rd);
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tcg_rn = cpu_reg(s, a->rn);
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if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
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/* some immediate field values are reserved */
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unallocated_encoding(s);
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return;
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fn(tcg_rd, tcg_rn, imm);
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if (set_cc) {
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gen_logic_CC(a->sf, tcg_rd);
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}
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if (!sf) {
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wmask &= 0xffffffff;
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}
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switch (opc) {
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case 0x3: /* ANDS */
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case 0x0: /* AND */
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tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
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is_and = true;
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break;
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case 0x1: /* ORR */
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tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
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break;
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case 0x2: /* EOR */
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tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
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break;
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default:
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assert(FALSE); /* must handle all above */
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break;
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}
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if (!sf && !is_and) {
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/* zero extend final result; we know we can skip this for AND
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* since the immediate had the high 32 bits clear.
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*/
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if (!a->sf) {
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tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
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}
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if (opc == 3) { /* ANDS */
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gen_logic_CC(sf, tcg_rd);
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}
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return true;
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}
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TRANS(AND_i, gen_rri_log, a, false, tcg_gen_andi_i64)
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TRANS(ORR_i, gen_rri_log, a, false, tcg_gen_ori_i64)
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TRANS(EOR_i, gen_rri_log, a, false, tcg_gen_xori_i64)
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TRANS(ANDS_i, gen_rri_log, a, true, tcg_gen_andi_i64)
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/*
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* Move wide (immediate)
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*
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@ -4618,9 +4585,6 @@ static void disas_extract(DisasContext *s, uint32_t insn)
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static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
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{
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switch (extract32(insn, 23, 6)) {
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case 0x24: /* Logical (immediate) */
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disas_logic_imm(s, insn);
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break;
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case 0x25: /* Move wide (immediate) */
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disas_movw_imm(s, insn);
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break;
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