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target-tricore: Add instructions of BRN opcode format 

Add instructions of BRN opcode format.
Add MASK_OP_BRN_DISP15_SEXT.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
master
Bastian Koppelmann 2014-10-17 17:46:29 +01:00
parent fc2ef4a391
commit 83c1bb1868
2 changed files with 27 additions and 0 deletions
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26
target-tricore/translate.c
View File

@ -568,6 +568,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
int r2 , int32_t constant , int32_t offset) int r2 , int32_t constant , int32_t offset)
{ {
TCGv temp; TCGv temp;
int n;
switch (opc) { switch (opc) {
/* SB-format jumps */ /* SB-format jumps */
@ -706,6 +707,20 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
} }
tcg_temp_free(temp); tcg_temp_free(temp);
break; break;
/* BRN format */
case OPCM_32_BRN_JTT:
n = MASK_OP_BRN_N(ctx->opcode);
temp = tcg_temp_new();
tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
} else {
gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
}
tcg_temp_free(temp);
break;
default: default:
printf("Branch Error at %x\n", ctx->pc); printf("Branch Error at %x\n", ctx->pc);
} }
@ -2371,6 +2386,11 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
op1 = MASK_OP_MAJOR(ctx->opcode); op1 = MASK_OP_MAJOR(ctx->opcode);
/* handle JNZ.T opcode only being 6 bit long */
if (unlikely((op1 & 0x3f) == OPCM_32_BRN_JTT)) {
op1 = OPCM_32_BRN_JTT;
}
switch (op1) { switch (op1) {
/* ABS-format */ /* ABS-format */
case OPCM_32_ABS_LDW: case OPCM_32_ABS_LDW:
@ -2504,6 +2524,12 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
r1 = MASK_OP_BRC_S1(ctx->opcode); r1 = MASK_OP_BRC_S1(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, const4, address); gen_compute_branch(ctx, op1, r1, 0, const4, address);
break; break;
/* BRN Format */
case OPCM_32_BRN_JTT:
address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
r1 = MASK_OP_BRN_S1(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, 0, address);
break;
} }
} }

1
target-tricore/tricore-opcodes.h
View File

@ -132,6 +132,7 @@
/* BRN Format */ /* BRN Format */
#define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31) #define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
#define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30) #define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
#define MASK_OP_BRN_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
#define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \ #define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \
(MASK_BITS_SHIFT(op, 7, 7) << 4)) (MASK_BITS_SHIFT(op, 7, 7) << 4))
#define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11) #define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11)