mirror of https://github.com/proxmox/mirror_qemu
target-arm: A64: Add simple SIMD 3-same floating point ops
Implement a simple subset of the SIMD 3-same floating point operations. This includes a common helper function used for both scalar and vector ops; FABD is the only currently implemented shared op. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>master
Peter Maydell
parent
1f8a73af12
commit
845ea09acc
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@ -5577,6 +5577,131 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
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}
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}
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/* Handle the 3-same-operands float operations; shared by the scalar
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* and vector encodings. The caller must filter out any encodings
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* not allocated for the encoding it is dealing with.
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*/
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static void handle_3same_float(DisasContext *s, int size, int elements,
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int fpopcode, int rd, int rn, int rm)
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{
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int pass;
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TCGv_ptr fpst = get_fpstatus_ptr();
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for (pass = 0; pass < elements; pass++) {
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if (size) {
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/* Double */
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TCGv_i64 tcg_op1 = tcg_temp_new_i64();
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TCGv_i64 tcg_op2 = tcg_temp_new_i64();
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TCGv_i64 tcg_res = tcg_temp_new_i64();
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read_vec_element(s, tcg_op1, rn, pass, MO_64);
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read_vec_element(s, tcg_op2, rm, pass, MO_64);
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switch (fpopcode) {
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case 0x18: /* FMAXNM */
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gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1a: /* FADD */
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gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1e: /* FMAX */
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gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x38: /* FMINNM */
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gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3a: /* FSUB */
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gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3e: /* FMIN */
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gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5b: /* FMUL */
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gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5f: /* FDIV */
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gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x7a: /* FABD */
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gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
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gen_helper_vfp_absd(tcg_res, tcg_res);
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break;
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default:
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g_assert_not_reached();
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}
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write_vec_element(s, tcg_res, rd, pass, MO_64);
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tcg_temp_free_i64(tcg_res);
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tcg_temp_free_i64(tcg_op1);
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tcg_temp_free_i64(tcg_op2);
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} else {
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/* Single */
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TCGv_i32 tcg_op1 = tcg_temp_new_i32();
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TCGv_i32 tcg_op2 = tcg_temp_new_i32();
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TCGv_i32 tcg_res = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
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read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
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switch (fpopcode) {
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case 0x1a: /* FADD */
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gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1e: /* FMAX */
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gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x18: /* FMAXNM */
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gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x38: /* FMINNM */
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gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3a: /* FSUB */
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gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3e: /* FMIN */
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gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5b: /* FMUL */
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gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5f: /* FDIV */
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gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x7a: /* FABD */
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gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
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gen_helper_vfp_abss(tcg_res, tcg_res);
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break;
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default:
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g_assert_not_reached();
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}
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if (elements == 1) {
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/* scalar single so clear high part */
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TCGv_i64 tcg_tmp = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(tcg_tmp, tcg_res);
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write_vec_element(s, tcg_tmp, rd, pass, MO_64);
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tcg_temp_free_i64(tcg_tmp);
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} else {
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write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
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}
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tcg_temp_free_i32(tcg_res);
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tcg_temp_free_i32(tcg_op1);
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tcg_temp_free_i32(tcg_op2);
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}
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}
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tcg_temp_free_ptr(fpst);
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if ((elements << size) < 4) {
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/* scalar, or non-quad vector op */
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clear_vec_high(s, rd);
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}
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}
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/* C3.6.11 AdvSIMD scalar three same
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* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
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* +-----+---+-----------+------+---+------+--------+---+------+------+
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@ -5605,15 +5730,19 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
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case 0x3f: /* FRSQRTS */
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case 0x5c: /* FCMGE */
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case 0x5d: /* FACGE */
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case 0x7a: /* FABD */
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case 0x7c: /* FCMGT */
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case 0x7d: /* FACGT */
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unsupported_encoding(s, insn);
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return;
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case 0x7a: /* FABD */
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm);
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return;
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}
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switch (opcode) {
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@ -6028,7 +6157,64 @@ static void disas_simd_3same_pair(DisasContext *s, uint32_t insn)
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/* Floating point op subgroup of C3.6.16. */
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static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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/* For floating point ops, the U, size[1] and opcode bits
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* together indicate the operation. size[0] indicates single
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* or double.
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*/
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int fpopcode = extract32(insn, 11, 5)
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| (extract32(insn, 23, 1) << 5)
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| (extract32(insn, 29, 1) << 6);
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int is_q = extract32(insn, 30, 1);
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int size = extract32(insn, 22, 1);
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int rm = extract32(insn, 16, 5);
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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int datasize = is_q ? 128 : 64;
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int esize = 32 << size;
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int elements = datasize / esize;
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if (size == 1 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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switch (fpopcode) {
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case 0x58: /* FMAXNMP */
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case 0x5a: /* FADDP */
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case 0x5e: /* FMAXP */
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case 0x78: /* FMINNMP */
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case 0x7e: /* FMINP */
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/* pairwise ops */
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unsupported_encoding(s, insn);
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return;
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case 0x1b: /* FMULX */
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case 0x1c: /* FCMEQ */
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case 0x1f: /* FRECPS */
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case 0x3f: /* FRSQRTS */
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case 0x5c: /* FCMGE */
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case 0x5d: /* FACGE */
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case 0x7c: /* FCMGT */
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case 0x7d: /* FACGT */
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case 0x19: /* FMLA */
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case 0x39: /* FMLS */
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unsupported_encoding(s, insn);
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return;
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case 0x18: /* FMAXNM */
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case 0x1a: /* FADD */
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case 0x1e: /* FMAX */
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case 0x38: /* FMINNM */
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case 0x3a: /* FSUB */
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case 0x3e: /* FMIN */
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case 0x5b: /* FMUL */
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case 0x5f: /* FDIV */
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case 0x7a: /* FABD */
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handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
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return;
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default:
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unallocated_encoding(s);
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return;
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}
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}
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/* Integer op subgroup of C3.6.16. */
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