mirror of https://github.com/proxmox/mirror_qemu
hw/misc: Introduce a model of Xilinx Versal's CFU_APB
Introduce a model of the software programming interface (CFU_APB) of Xilinx Versal's Configuration Frame Unit. Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230831165701.2016397-3-francisco.iglesias@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Francisco Iglesias
Peter Maydell
parent
5a8559e2cc
commit
86d916c621
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@ -1031,6 +1031,8 @@ M: Francisco Iglesias <francisco.iglesias@amd.com>
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S: Maintained
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F: hw/misc/xlnx-cfi-if.c
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F: include/hw/misc/xlnx-cfi-if.h
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F: hw/misc/xlnx-versal-cfu.c
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F: include/hw/misc/xlnx-versal-cfu.h
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STM32F100
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M: Alexandre Iooss <erdnaxe@crans.org>
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@ -98,6 +98,7 @@ specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
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system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
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'xlnx-versal-xramc.c',
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'xlnx-versal-pmc-iou-slcr.c',
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'xlnx-versal-cfu.c',
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'xlnx-cfi-if.c',
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))
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system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
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@ -0,0 +1,380 @@
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/*
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* QEMU model of the CFU Configuration Unit.
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*
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* Copyright (C) 2023, Advanced Micro Devices, Inc.
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*
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* Written by Edgar E. Iglesias <edgar.iglesias@gmail.com>,
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* Sai Pavan Boddu <sai.pavan.boddu@amd.com>,
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* Francisco Iglesias <francisco.iglesias@amd.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "hw/irq.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qemu/units.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/misc/xlnx-versal-cfu.h"
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#ifndef XLNX_VERSAL_CFU_APB_ERR_DEBUG
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#define XLNX_VERSAL_CFU_APB_ERR_DEBUG 0
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#endif
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#define KEYHOLE_STREAM_4K (4 * KiB)
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#define KEYHOLE_STREAM_256K (256 * KiB)
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#define CFRAME_BROADCAST_ROW 0x1F
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bool update_wfifo(hwaddr addr, uint64_t value,
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uint32_t *wfifo, uint32_t *wfifo_ret)
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{
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unsigned int idx = extract32(addr, 2, 2);
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wfifo[idx] = value;
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if (idx == 3) {
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memcpy(wfifo_ret, wfifo, WFIFO_SZ * sizeof(uint32_t));
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memset(wfifo, 0, WFIFO_SZ * sizeof(uint32_t));
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return true;
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}
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return false;
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}
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static void cfu_imr_update_irq(XlnxVersalCFUAPB *s)
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{
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bool pending = s->regs[R_CFU_ISR] & ~s->regs[R_CFU_IMR];
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qemu_set_irq(s->irq_cfu_imr, pending);
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}
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static void cfu_isr_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);
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cfu_imr_update_irq(s);
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}
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static uint64_t cfu_ier_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);
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uint32_t val = val64;
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s->regs[R_CFU_IMR] &= ~val;
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cfu_imr_update_irq(s);
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return 0;
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}
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static uint64_t cfu_idr_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);
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uint32_t val = val64;
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s->regs[R_CFU_IMR] |= val;
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cfu_imr_update_irq(s);
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return 0;
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}
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static uint64_t cfu_itr_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);
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uint32_t val = val64;
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s->regs[R_CFU_ISR] |= val;
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cfu_imr_update_irq(s);
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return 0;
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}
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static void cfu_fgcr_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);
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uint32_t val = (uint32_t)val64;
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/* Do a scan. It always looks good. */
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if (FIELD_EX32(val, CFU_FGCR, SC_HBC_TRIGGER)) {
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ARRAY_FIELD_DP32(s->regs, CFU_STATUS, SCAN_CLEAR_PASS, 1);
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ARRAY_FIELD_DP32(s->regs, CFU_STATUS, SCAN_CLEAR_DONE, 1);
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}
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}
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static const RegisterAccessInfo cfu_apb_regs_info[] = {
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{ .name = "CFU_ISR", .addr = A_CFU_ISR,
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.rsvd = 0xfffffc00,
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.w1c = 0x3ff,
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.post_write = cfu_isr_postw,
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},{ .name = "CFU_IMR", .addr = A_CFU_IMR,
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.reset = 0x3ff,
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.rsvd = 0xfffffc00,
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.ro = 0x3ff,
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},{ .name = "CFU_IER", .addr = A_CFU_IER,
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.rsvd = 0xfffffc00,
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.pre_write = cfu_ier_prew,
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},{ .name = "CFU_IDR", .addr = A_CFU_IDR,
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.rsvd = 0xfffffc00,
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.pre_write = cfu_idr_prew,
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},{ .name = "CFU_ITR", .addr = A_CFU_ITR,
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.rsvd = 0xfffffc00,
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.pre_write = cfu_itr_prew,
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},{ .name = "CFU_PROTECT", .addr = A_CFU_PROTECT,
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.reset = 0x1,
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},{ .name = "CFU_FGCR", .addr = A_CFU_FGCR,
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.rsvd = 0xffff8000,
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.post_write = cfu_fgcr_postw,
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},{ .name = "CFU_CTL", .addr = A_CFU_CTL,
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.rsvd = 0xffff0000,
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},{ .name = "CFU_CRAM_RW", .addr = A_CFU_CRAM_RW,
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.reset = 0x401f7d9,
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.rsvd = 0xf8000000,
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},{ .name = "CFU_MASK", .addr = A_CFU_MASK,
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},{ .name = "CFU_CRC_EXPECT", .addr = A_CFU_CRC_EXPECT,
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},{ .name = "CFU_CFRAME_LEFT_T0", .addr = A_CFU_CFRAME_LEFT_T0,
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.rsvd = 0xfff00000,
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},{ .name = "CFU_CFRAME_LEFT_T1", .addr = A_CFU_CFRAME_LEFT_T1,
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.rsvd = 0xfff00000,
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},{ .name = "CFU_CFRAME_LEFT_T2", .addr = A_CFU_CFRAME_LEFT_T2,
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.rsvd = 0xfff00000,
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},{ .name = "CFU_ROW_RANGE", .addr = A_CFU_ROW_RANGE,
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.rsvd = 0xffffffc0,
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.ro = 0x3f,
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},{ .name = "CFU_STATUS", .addr = A_CFU_STATUS,
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.rsvd = 0x80000000,
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.ro = 0x7fffffff,
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},{ .name = "CFU_INTERNAL_STATUS", .addr = A_CFU_INTERNAL_STATUS,
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.rsvd = 0xff800000,
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.ro = 0x7fffff,
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},{ .name = "CFU_QWORD_CNT", .addr = A_CFU_QWORD_CNT,
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.ro = 0xffffffff,
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},{ .name = "CFU_CRC_LIVE", .addr = A_CFU_CRC_LIVE,
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.ro = 0xffffffff,
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},{ .name = "CFU_PENDING_READ_CNT", .addr = A_CFU_PENDING_READ_CNT,
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.rsvd = 0xfe000000,
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.ro = 0x1ffffff,
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},{ .name = "CFU_FDRI_CNT", .addr = A_CFU_FDRI_CNT,
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.ro = 0xffffffff,
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},{ .name = "CFU_ECO1", .addr = A_CFU_ECO1,
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},{ .name = "CFU_ECO2", .addr = A_CFU_ECO2,
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}
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};
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static void cfu_apb_reset(DeviceState *dev)
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{
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XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(dev);
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
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register_reset(&s->regs_info[i]);
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}
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memset(s->wfifo, 0, WFIFO_SZ * sizeof(uint32_t));
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s->regs[R_CFU_STATUS] |= R_CFU_STATUS_HC_COMPLETE_MASK;
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cfu_imr_update_irq(s);
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}
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static const MemoryRegionOps cfu_apb_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void cfu_transfer_cfi_packet(XlnxVersalCFUAPB *s, uint8_t row_addr,
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XlnxCfiPacket *pkt)
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{
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if (row_addr == CFRAME_BROADCAST_ROW) {
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for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) {
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if (s->cfg.cframe[i]) {
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xlnx_cfi_transfer_packet(s->cfg.cframe[i], pkt);
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}
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}
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} else {
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assert(row_addr < ARRAY_SIZE(s->cfg.cframe));
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if (s->cfg.cframe[row_addr]) {
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xlnx_cfi_transfer_packet(s->cfg.cframe[row_addr], pkt);
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}
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}
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}
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static uint64_t cfu_stream_read(void *opaque, hwaddr addr, unsigned size)
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{
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
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HWADDR_PRIx "\n", __func__, addr);
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return 0;
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}
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static void cfu_stream_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(opaque);
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uint32_t wfifo[WFIFO_SZ];
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if (update_wfifo(addr, value, s->wfifo, wfifo)) {
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uint8_t packet_type, row_addr, reg_addr;
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packet_type = extract32(wfifo[0], 24, 8);
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row_addr = extract32(wfifo[0], 16, 5);
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reg_addr = extract32(wfifo[0], 8, 6);
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/* Compressed bitstreams are not supported yet. */
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if (ARRAY_FIELD_EX32(s->regs, CFU_CTL, DECOMPRESS) == 0) {
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if (s->regs[R_CFU_FDRI_CNT]) {
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XlnxCfiPacket pkt = {
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.reg_addr = CFRAME_FDRI,
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.data[0] = wfifo[0],
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.data[1] = wfifo[1],
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.data[2] = wfifo[2],
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.data[3] = wfifo[3]
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};
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cfu_transfer_cfi_packet(s, s->fdri_row_addr, &pkt);
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s->regs[R_CFU_FDRI_CNT]--;
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} else if (packet_type == PACKET_TYPE_CFU &&
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reg_addr == CFRAME_FDRI) {
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/* Load R_CFU_FDRI_CNT, must be multiple of 25 */
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s->regs[R_CFU_FDRI_CNT] = wfifo[1];
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/* Store target row_addr */
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s->fdri_row_addr = row_addr;
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if (wfifo[1] % 25 != 0) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"CFU FDRI_CNT is not loaded with "
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"a multiple of 25 value\n");
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}
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} else if (packet_type == PACKET_TYPE_CFRAME) {
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XlnxCfiPacket pkt = {
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.reg_addr = reg_addr,
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.data[0] = wfifo[1],
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.data[1] = wfifo[2],
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.data[2] = wfifo[3],
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};
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cfu_transfer_cfi_packet(s, row_addr, &pkt);
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}
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}
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}
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}
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static const MemoryRegionOps cfu_stream_ops = {
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.read = cfu_stream_read,
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.write = cfu_stream_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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};
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static void cfu_apb_init(Object *obj)
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{
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XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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RegisterInfoArray *reg_array;
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unsigned int i;
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char *name;
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memory_region_init(&s->iomem, obj, TYPE_XLNX_VERSAL_CFU_APB, R_MAX * 4);
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reg_array =
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register_init_block32(DEVICE(obj), cfu_apb_regs_info,
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ARRAY_SIZE(cfu_apb_regs_info),
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s->regs_info, s->regs,
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&cfu_apb_ops,
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XLNX_VERSAL_CFU_APB_ERR_DEBUG,
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R_MAX * 4);
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memory_region_add_subregion(&s->iomem,
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0x0,
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®_array->mem);
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sysbus_init_mmio(sbd, &s->iomem);
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for (i = 0; i < NUM_STREAM; i++) {
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name = g_strdup_printf(TYPE_XLNX_VERSAL_CFU_APB "-stream%d", i);
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memory_region_init_io(&s->iomem_stream[i], obj, &cfu_stream_ops, s,
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name, i == 0 ? KEYHOLE_STREAM_4K :
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KEYHOLE_STREAM_256K);
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sysbus_init_mmio(sbd, &s->iomem_stream[i]);
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g_free(name);
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}
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sysbus_init_irq(sbd, &s->irq_cfu_imr);
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}
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static Property cfu_props[] = {
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DEFINE_PROP_LINK("cframe0", XlnxVersalCFUAPB, cfg.cframe[0],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe1", XlnxVersalCFUAPB, cfg.cframe[1],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe2", XlnxVersalCFUAPB, cfg.cframe[2],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe3", XlnxVersalCFUAPB, cfg.cframe[3],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe4", XlnxVersalCFUAPB, cfg.cframe[4],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe5", XlnxVersalCFUAPB, cfg.cframe[5],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe6", XlnxVersalCFUAPB, cfg.cframe[6],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe7", XlnxVersalCFUAPB, cfg.cframe[7],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe8", XlnxVersalCFUAPB, cfg.cframe[8],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe9", XlnxVersalCFUAPB, cfg.cframe[9],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe10", XlnxVersalCFUAPB, cfg.cframe[10],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe11", XlnxVersalCFUAPB, cfg.cframe[11],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe12", XlnxVersalCFUAPB, cfg.cframe[12],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe13", XlnxVersalCFUAPB, cfg.cframe[13],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_LINK("cframe14", XlnxVersalCFUAPB, cfg.cframe[14],
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TYPE_XLNX_CFI_IF, XlnxCfiIf *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static const VMStateDescription vmstate_cfu_apb = {
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.name = TYPE_XLNX_VERSAL_CFU_APB,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFUAPB, 4),
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VMSTATE_UINT32_ARRAY(regs, XlnxVersalCFUAPB, R_MAX),
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VMSTATE_UINT8(fdri_row_addr, XlnxVersalCFUAPB),
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VMSTATE_END_OF_LIST(),
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}
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};
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static void cfu_apb_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = cfu_apb_reset;
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dc->vmsd = &vmstate_cfu_apb;
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device_class_set_props(dc, cfu_props);
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}
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|
||||
static const TypeInfo cfu_apb_info = {
|
||||
.name = TYPE_XLNX_VERSAL_CFU_APB,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(XlnxVersalCFUAPB),
|
||||
.class_init = cfu_apb_class_init,
|
||||
.instance_init = cfu_apb_init,
|
||||
.interfaces = (InterfaceInfo[]) {
|
||||
{ TYPE_XLNX_CFI_IF },
|
||||
{ }
|
||||
}
|
||||
};
|
||||
|
||||
static void cfu_apb_register_types(void)
|
||||
{
|
||||
type_register_static(&cfu_apb_info);
|
||||
}
|
||||
|
||||
type_init(cfu_apb_register_types)
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* QEMU model of the CFU Configuration Unit.
|
||||
*
|
||||
* Copyright (C) 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Written by Francisco Iglesias <francisco.iglesias@amd.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* References:
|
||||
* [1] Versal ACAP Technical Reference Manual,
|
||||
* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
|
||||
*
|
||||
* [2] Versal ACAP Register Reference,
|
||||
* https://www.xilinx.com/htmldocs/registers/am012/am012-versal-register-reference.html
|
||||
*/
|
||||
#ifndef HW_MISC_XLNX_VERSAL_CFU_APB_H
|
||||
#define HW_MISC_XLNX_VERSAL_CFU_APB_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/register.h"
|
||||
#include "hw/misc/xlnx-cfi-if.h"
|
||||
|
||||
#define TYPE_XLNX_VERSAL_CFU_APB "xlnx,versal-cfu-apb"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUAPB, XLNX_VERSAL_CFU_APB)
|
||||
|
||||
REG32(CFU_ISR, 0x0)
|
||||
FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
|
||||
FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
|
||||
FIELD(CFU_ISR, SLVERR, 7, 1)
|
||||
FIELD(CFU_ISR, DECOMP_ERROR, 6, 1)
|
||||
FIELD(CFU_ISR, BAD_CFI_PACKET, 5, 1)
|
||||
FIELD(CFU_ISR, AXI_ALIGN_ERROR, 4, 1)
|
||||
FIELD(CFU_ISR, CFI_ROW_ERROR, 3, 1)
|
||||
FIELD(CFU_ISR, CRC32_ERROR, 2, 1)
|
||||
FIELD(CFU_ISR, CRC8_ERROR, 1, 1)
|
||||
FIELD(CFU_ISR, SEU_ENDOFCALIB, 0, 1)
|
||||
REG32(CFU_IMR, 0x4)
|
||||
FIELD(CFU_IMR, USR_GTS_EVENT, 9, 1)
|
||||
FIELD(CFU_IMR, USR_GSR_EVENT, 8, 1)
|
||||
FIELD(CFU_IMR, SLVERR, 7, 1)
|
||||
FIELD(CFU_IMR, DECOMP_ERROR, 6, 1)
|
||||
FIELD(CFU_IMR, BAD_CFI_PACKET, 5, 1)
|
||||
FIELD(CFU_IMR, AXI_ALIGN_ERROR, 4, 1)
|
||||
FIELD(CFU_IMR, CFI_ROW_ERROR, 3, 1)
|
||||
FIELD(CFU_IMR, CRC32_ERROR, 2, 1)
|
||||
FIELD(CFU_IMR, CRC8_ERROR, 1, 1)
|
||||
FIELD(CFU_IMR, SEU_ENDOFCALIB, 0, 1)
|
||||
REG32(CFU_IER, 0x8)
|
||||
FIELD(CFU_IER, USR_GTS_EVENT, 9, 1)
|
||||
FIELD(CFU_IER, USR_GSR_EVENT, 8, 1)
|
||||
FIELD(CFU_IER, SLVERR, 7, 1)
|
||||
FIELD(CFU_IER, DECOMP_ERROR, 6, 1)
|
||||
FIELD(CFU_IER, BAD_CFI_PACKET, 5, 1)
|
||||
FIELD(CFU_IER, AXI_ALIGN_ERROR, 4, 1)
|
||||
FIELD(CFU_IER, CFI_ROW_ERROR, 3, 1)
|
||||
FIELD(CFU_IER, CRC32_ERROR, 2, 1)
|
||||
FIELD(CFU_IER, CRC8_ERROR, 1, 1)
|
||||
FIELD(CFU_IER, SEU_ENDOFCALIB, 0, 1)
|
||||
REG32(CFU_IDR, 0xc)
|
||||
FIELD(CFU_IDR, USR_GTS_EVENT, 9, 1)
|
||||
FIELD(CFU_IDR, USR_GSR_EVENT, 8, 1)
|
||||
FIELD(CFU_IDR, SLVERR, 7, 1)
|
||||
FIELD(CFU_IDR, DECOMP_ERROR, 6, 1)
|
||||
FIELD(CFU_IDR, BAD_CFI_PACKET, 5, 1)
|
||||
FIELD(CFU_IDR, AXI_ALIGN_ERROR, 4, 1)
|
||||
FIELD(CFU_IDR, CFI_ROW_ERROR, 3, 1)
|
||||
FIELD(CFU_IDR, CRC32_ERROR, 2, 1)
|
||||
FIELD(CFU_IDR, CRC8_ERROR, 1, 1)
|
||||
FIELD(CFU_IDR, SEU_ENDOFCALIB, 0, 1)
|
||||
REG32(CFU_ITR, 0x10)
|
||||
FIELD(CFU_ITR, USR_GTS_EVENT, 9, 1)
|
||||
FIELD(CFU_ITR, USR_GSR_EVENT, 8, 1)
|
||||
FIELD(CFU_ITR, SLVERR, 7, 1)
|
||||
FIELD(CFU_ITR, DECOMP_ERROR, 6, 1)
|
||||
FIELD(CFU_ITR, BAD_CFI_PACKET, 5, 1)
|
||||
FIELD(CFU_ITR, AXI_ALIGN_ERROR, 4, 1)
|
||||
FIELD(CFU_ITR, CFI_ROW_ERROR, 3, 1)
|
||||
FIELD(CFU_ITR, CRC32_ERROR, 2, 1)
|
||||
FIELD(CFU_ITR, CRC8_ERROR, 1, 1)
|
||||
FIELD(CFU_ITR, SEU_ENDOFCALIB, 0, 1)
|
||||
REG32(CFU_PROTECT, 0x14)
|
||||
FIELD(CFU_PROTECT, ACTIVE, 0, 1)
|
||||
REG32(CFU_FGCR, 0x18)
|
||||
FIELD(CFU_FGCR, GCLK_CAL, 14, 1)
|
||||
FIELD(CFU_FGCR, SC_HBC_TRIGGER, 13, 1)
|
||||
FIELD(CFU_FGCR, GLOW, 12, 1)
|
||||
FIELD(CFU_FGCR, GPWRDWN, 11, 1)
|
||||
FIELD(CFU_FGCR, GCAP, 10, 1)
|
||||
FIELD(CFU_FGCR, GSCWE, 9, 1)
|
||||
FIELD(CFU_FGCR, GHIGH_B, 8, 1)
|
||||
FIELD(CFU_FGCR, GMC_B, 7, 1)
|
||||
FIELD(CFU_FGCR, GWE, 6, 1)
|
||||
FIELD(CFU_FGCR, GRESTORE, 5, 1)
|
||||
FIELD(CFU_FGCR, GTS_CFG_B, 4, 1)
|
||||
FIELD(CFU_FGCR, GLUTMASK, 3, 1)
|
||||
FIELD(CFU_FGCR, EN_GLOBS_B, 2, 1)
|
||||
FIELD(CFU_FGCR, EOS, 1, 1)
|
||||
FIELD(CFU_FGCR, INIT_COMPLETE, 0, 1)
|
||||
REG32(CFU_CTL, 0x1c)
|
||||
FIELD(CFU_CTL, GSR_GSC, 15, 1)
|
||||
FIELD(CFU_CTL, SLVERR_EN, 14, 1)
|
||||
FIELD(CFU_CTL, CRC32_RESET, 13, 1)
|
||||
FIELD(CFU_CTL, AXI_ERROR_EN, 12, 1)
|
||||
FIELD(CFU_CTL, FLUSH_AXI, 11, 1)
|
||||
FIELD(CFU_CTL, SSI_PER_SLR_PR, 10, 1)
|
||||
FIELD(CFU_CTL, GCAP_CLK_EN, 9, 1)
|
||||
FIELD(CFU_CTL, STATUS_SYNC_DISABLE, 8, 1)
|
||||
FIELD(CFU_CTL, IGNORE_CFI_ERROR, 7, 1)
|
||||
FIELD(CFU_CTL, CFRAME_DISABLE, 6, 1)
|
||||
FIELD(CFU_CTL, QWORD_CNT_RESET, 5, 1)
|
||||
FIELD(CFU_CTL, CRC8_DISABLE, 4, 1)
|
||||
FIELD(CFU_CTL, CRC32_CHECK, 3, 1)
|
||||
FIELD(CFU_CTL, DECOMPRESS, 2, 1)
|
||||
FIELD(CFU_CTL, SEU_GO, 1, 1)
|
||||
FIELD(CFU_CTL, CFI_LOCAL_RESET, 0, 1)
|
||||
REG32(CFU_CRAM_RW, 0x20)
|
||||
FIELD(CFU_CRAM_RW, RFIFO_AFULL_DEPTH, 18, 9)
|
||||
FIELD(CFU_CRAM_RW, RD_WAVE_CNT_LEFT, 12, 6)
|
||||
FIELD(CFU_CRAM_RW, RD_WAVE_CNT, 6, 6)
|
||||
FIELD(CFU_CRAM_RW, WR_WAVE_CNT, 0, 6)
|
||||
REG32(CFU_MASK, 0x28)
|
||||
REG32(CFU_CRC_EXPECT, 0x2c)
|
||||
REG32(CFU_CFRAME_LEFT_T0, 0x60)
|
||||
FIELD(CFU_CFRAME_LEFT_T0, NUM, 0, 20)
|
||||
REG32(CFU_CFRAME_LEFT_T1, 0x64)
|
||||
FIELD(CFU_CFRAME_LEFT_T1, NUM, 0, 20)
|
||||
REG32(CFU_CFRAME_LEFT_T2, 0x68)
|
||||
FIELD(CFU_CFRAME_LEFT_T2, NUM, 0, 20)
|
||||
REG32(CFU_ROW_RANGE, 0x6c)
|
||||
FIELD(CFU_ROW_RANGE, HALF_FSR, 5, 1)
|
||||
FIELD(CFU_ROW_RANGE, NUM, 0, 5)
|
||||
REG32(CFU_STATUS, 0x100)
|
||||
FIELD(CFU_STATUS, SEU_WRITE_ERROR, 30, 1)
|
||||
FIELD(CFU_STATUS, FRCNT_ERROR, 29, 1)
|
||||
FIELD(CFU_STATUS, RSVD_ERROR, 28, 1)
|
||||
FIELD(CFU_STATUS, FDRO_ERROR, 27, 1)
|
||||
FIELD(CFU_STATUS, FDRI_ERROR, 26, 1)
|
||||
FIELD(CFU_STATUS, FDRI_READ_ERROR, 25, 1)
|
||||
FIELD(CFU_STATUS, READ_FDRI_ERROR, 24, 1)
|
||||
FIELD(CFU_STATUS, READ_SFR_ERROR, 23, 1)
|
||||
FIELD(CFU_STATUS, READ_STREAM_ERROR, 22, 1)
|
||||
FIELD(CFU_STATUS, UNKNOWN_STREAM_PKT, 21, 1)
|
||||
FIELD(CFU_STATUS, USR_GTS, 20, 1)
|
||||
FIELD(CFU_STATUS, USR_GSR, 19, 1)
|
||||
FIELD(CFU_STATUS, AXI_BAD_WSTRB, 18, 1)
|
||||
FIELD(CFU_STATUS, AXI_BAD_AR_SIZE, 17, 1)
|
||||
FIELD(CFU_STATUS, AXI_BAD_AW_SIZE, 16, 1)
|
||||
FIELD(CFU_STATUS, AXI_BAD_ARADDR, 15, 1)
|
||||
FIELD(CFU_STATUS, AXI_BAD_AWADDR, 14, 1)
|
||||
FIELD(CFU_STATUS, SCAN_CLEAR_PASS, 13, 1)
|
||||
FIELD(CFU_STATUS, HC_SEC_ERROR, 12, 1)
|
||||
FIELD(CFU_STATUS, GHIGH_B_ISHIGH, 11, 1)
|
||||
FIELD(CFU_STATUS, GHIGH_B_ISLOW, 10, 1)
|
||||
FIELD(CFU_STATUS, GMC_B_ISHIGH, 9, 1)
|
||||
FIELD(CFU_STATUS, GMC_B_ISLOW, 8, 1)
|
||||
FIELD(CFU_STATUS, GPWRDWN_B_ISHIGH, 7, 1)
|
||||
FIELD(CFU_STATUS, CFI_SEU_CRC_ERROR, 6, 1)
|
||||
FIELD(CFU_STATUS, CFI_SEU_ECC_ERROR, 5, 1)
|
||||
FIELD(CFU_STATUS, CFI_SEU_HEARTBEAT, 4, 1)
|
||||
FIELD(CFU_STATUS, SCAN_CLEAR_DONE, 3, 1)
|
||||
FIELD(CFU_STATUS, HC_COMPLETE, 2, 1)
|
||||
FIELD(CFU_STATUS, CFI_CFRAME_BUSY, 1, 1)
|
||||
FIELD(CFU_STATUS, CFU_STREAM_BUSY, 0, 1)
|
||||
REG32(CFU_INTERNAL_STATUS, 0x104)
|
||||
FIELD(CFU_INTERNAL_STATUS, SSI_EOS, 22, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, SSI_GWE, 21, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, RFIFO_EMPTY, 20, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, RFIFO_FULL, 19, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, SEL_SFR, 18, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, STREAM_CFRAME, 17, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, FDRI_PHASE, 16, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, CFI_PIPE_EN, 15, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, AWFIFO_DCNT, 10, 5)
|
||||
FIELD(CFU_INTERNAL_STATUS, WFIFO_DCNT, 5, 5)
|
||||
FIELD(CFU_INTERNAL_STATUS, REPAIR_BUSY, 4, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, TRIMU_BUSY, 3, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, TRIMB_BUSY, 2, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, HCLEANR_BUSY, 1, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, HCLEAN_BUSY, 0, 1)
|
||||
REG32(CFU_QWORD_CNT, 0x108)
|
||||
REG32(CFU_CRC_LIVE, 0x10c)
|
||||
REG32(CFU_PENDING_READ_CNT, 0x110)
|
||||
FIELD(CFU_PENDING_READ_CNT, NUM, 0, 25)
|
||||
REG32(CFU_FDRI_CNT, 0x114)
|
||||
REG32(CFU_ECO1, 0x118)
|
||||
REG32(CFU_ECO2, 0x11c)
|
||||
|
||||
#define R_MAX (R_CFU_ECO2 + 1)
|
||||
|
||||
#define NUM_STREAM 2
|
||||
#define WFIFO_SZ 4
|
||||
|
||||
struct XlnxVersalCFUAPB {
|
||||
SysBusDevice parent_obj;
|
||||
MemoryRegion iomem;
|
||||
MemoryRegion iomem_stream[NUM_STREAM];
|
||||
qemu_irq irq_cfu_imr;
|
||||
|
||||
/* 128-bit wfifo. */
|
||||
uint32_t wfifo[WFIFO_SZ];
|
||||
|
||||
uint32_t regs[R_MAX];
|
||||
RegisterInfo regs_info[R_MAX];
|
||||
|
||||
uint8_t fdri_row_addr;
|
||||
|
||||
struct {
|
||||
XlnxCfiIf *cframe[15];
|
||||
} cfg;
|
||||
};
|
||||
|
||||
/**
|
||||
* This is a helper function for updating a CFI data write fifo, an array of 4
|
||||
* uint32_t and 128 bits of data that are allowed to be written through 4
|
||||
* sequential 32 bit accesses. After the last index has been written into the
|
||||
* write fifo (wfifo), the data is copied to and returned in a secondary fifo
|
||||
* provided to the function (wfifo_ret), and the write fifo is cleared
|
||||
* (zeroized).
|
||||
*
|
||||
* @addr: the address used when calculating the wfifo array index to update
|
||||
* @value: the value to write into the wfifo array
|
||||
* @wfifo: the wfifo to update
|
||||
* @wfifo_out: will return the wfifo data when all 128 bits have been written
|
||||
*
|
||||
* @return: true if all 128 bits have been updated.
|
||||
*/
|
||||
bool update_wfifo(hwaddr addr, uint64_t value,
|
||||
uint32_t *wfifo, uint32_t *wfifo_ret);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue