mirror of https://github.com/proxmox/mirror_qemu
target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
The bitmanipulation ISA extensions will be ratified as individual small extension packages instead of a large B-extension. The first new instructions through the door (these have completed public review) are Zb[abcs]. This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for these in target/riscv/cpu.[ch]. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>master
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@ -617,6 +617,10 @@ static Property riscv_cpu_properties[] = {
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DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
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/* This is experimental so mark with 'x-' */
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DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
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DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
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DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
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DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
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DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
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DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
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DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
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DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
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@ -293,6 +293,10 @@ struct RISCVCPU {
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bool ext_u;
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bool ext_h;
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bool ext_v;
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bool ext_zba;
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bool ext_zbb;
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bool ext_zbc;
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bool ext_zbs;
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bool ext_counters;
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bool ext_ifencei;
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bool ext_icsr;
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