mirror of https://github.com/proxmox/mirror_qemu
tcg/arm: Support unaligned access for softmmu
From armv6, the architecture supports unaligned accesses. All we need to do is perform the correct alignment check in tcg_out_tlb_read. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>master
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367d43d85b
commit
8821ec2323
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@ -1396,16 +1396,9 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
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int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write));
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: offsetof(CPUTLBEntry, addr_write));
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int fast_off = TLB_MASK_TABLE_OFS(mem_index);
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int fast_off = TLB_MASK_TABLE_OFS(mem_index);
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unsigned s_bits = opc & MO_SIZE;
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unsigned s_mask = (1 << (opc & MO_SIZE)) - 1;
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unsigned a_bits = get_alignment_bits(opc);
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unsigned a_mask = (1 << get_alignment_bits(opc)) - 1;
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TCGReg t_addr;
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/*
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* We don't support inline unaligned acceses, but we can easily
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* support overalignment checks.
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*/
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if (a_bits < s_bits) {
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a_bits = s_bits;
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}
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/* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */
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/* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
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@ -1440,27 +1433,35 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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/*
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/*
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* Check alignment, check comparators.
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* Check alignment, check comparators.
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* Do this in no more than 3 insns. Use MOVW for v7, if possible,
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* Do this in 2-4 insns. Use MOVW for v7, if possible,
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* to reduce the number of sequential conditional instructions.
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* to reduce the number of sequential conditional instructions.
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* Almost all guests have at least 4k pages, which means that we need
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* Almost all guests have at least 4k pages, which means that we need
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* to clear at least 9 bits even for an 8-byte memory, which means it
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* to clear at least 9 bits even for an 8-byte memory, which means it
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* isn't worth checking for an immediate operand for BIC.
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* isn't worth checking for an immediate operand for BIC.
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*
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* For unaligned accesses, test the page of the last unit of alignment.
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* This leaves the least significant alignment bits unchanged, and of
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* course must be zero.
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*/
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*/
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t_addr = addrlo;
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if (a_mask < s_mask) {
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t_addr = TCG_REG_R0;
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr,
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addrlo, s_mask - a_mask);
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}
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if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) {
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if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) {
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tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1));
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tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mask));
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tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);
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tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
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tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
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addrlo, TCG_REG_TMP, 0);
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t_addr, TCG_REG_TMP, 0);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
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} else {
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} else {
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if (a_bits) {
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if (a_mask) {
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo,
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tcg_debug_assert(a_mask <= 0xff);
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(1 << a_bits) - 1);
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
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}
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}
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo,
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr,
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SHIFT_IMM_LSR(TARGET_PAGE_BITS));
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SHIFT_IMM_LSR(TARGET_PAGE_BITS));
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tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP,
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tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP,
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0, TCG_REG_R2, TCG_REG_TMP,
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0, TCG_REG_R2, TCG_REG_TMP,
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SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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}
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}
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