From 8a14d31b00ae82ed430806bac96962b73fe6967f Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 7 Mar 2019 18:05:19 +0000 Subject: [PATCH] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order When VSX support was initially added, the fpr registers were added at offset 0 of the VSR register and the vsrl registers were added at offset 1. This is in contrast to the VMX registers (the last 32 VSX registers) which are stored in host-endian order. Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also stored in host endian order to match the VMX registers. This ensures that TCG vector operations involving mixed VMX and VSX registers will function correctly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20190307180520.13868-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson --- target/ppc/cpu.h | 4 ++-- target/ppc/internal.h | 8 ++++---- target/ppc/machine.c | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 7e18866ee2..612dd05e94 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2585,7 +2585,7 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx) static inline int fpr_offset(int i) { - return offsetof(CPUPPCState, vsr[i].u64[0]); + return offsetof(CPUPPCState, vsr[i].VsrD(0)); } static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) @@ -2595,7 +2595,7 @@ static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) static inline int vsrl_offset(int i) { - return offsetof(CPUPPCState, vsr[i].u64[1]); + return offsetof(CPUPPCState, vsr[i].VsrD(1)); } static inline int vsr_full_offset(int i) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 3ebbdf4da4..fb6f64ed1e 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -206,14 +206,14 @@ EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6); static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - vsr->VsrD(0) = env->vsr[n].u64[0]; - vsr->VsrD(1) = env->vsr[n].u64[1]; + vsr->VsrD(0) = env->vsr[n].VsrD(0); + vsr->VsrD(1) = env->vsr[n].VsrD(1); } static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - env->vsr[n].u64[0] = vsr->VsrD(0); - env->vsr[n].u64[1] = vsr->VsrD(1); + env->vsr[n].VsrD(0) = vsr->VsrD(0); + env->vsr[n].VsrD(1) = vsr->VsrD(1); } void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 756b6d2971..a92d0ad3a3 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -150,7 +150,7 @@ static int get_fpr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v = pv; - v->u64[0] = qemu_get_be64(f); + v->VsrD(0) = qemu_get_be64(f); return 0; } @@ -160,7 +160,7 @@ static int put_fpr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v = pv; - qemu_put_be64(f, v->u64[0]); + qemu_put_be64(f, v->VsrD(0)); return 0; } @@ -181,7 +181,7 @@ static int get_vsr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v = pv; - v->u64[1] = qemu_get_be64(f); + v->VsrD(1) = qemu_get_be64(f); return 0; } @@ -191,7 +191,7 @@ static int put_vsr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v = pv; - qemu_put_be64(f, v->u64[1]); + qemu_put_be64(f, v->VsrD(1)); return 0; }