mirror of https://github.com/proxmox/mirror_qemu
ppc: Move DFP ops out of translate.c
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>master
parent
4083de6b53
commit
8b25cdd371
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@ -7560,210 +7560,7 @@ static void gen_xxsldwi(DisasContext *ctx)
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tcg_temp_free_i64(xtl);
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}
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/*** Decimal Floating Point ***/
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static inline TCGv_ptr gen_fprp_ptr(int reg)
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{
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TCGv_ptr r = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
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return r;
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}
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#define GEN_DFP_T_A_B_Rc(name) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr rd, ra, rb; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->nip - 4); \
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rd = gen_fprp_ptr(rD(ctx->opcode)); \
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ra = gen_fprp_ptr(rA(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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gen_helper_##name(cpu_env, rd, ra, rb); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rd); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_ptr(rb); \
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}
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#define GEN_DFP_BF_A_B(name) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr ra, rb; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->nip - 4); \
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ra = gen_fprp_ptr(rA(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
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cpu_env, ra, rb); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_ptr(rb); \
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}
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#define GEN_DFP_BF_A_DCM(name) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr ra; \
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TCGv_i32 dcm; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->nip - 4); \
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ra = gen_fprp_ptr(rA(ctx->opcode)); \
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dcm = tcg_const_i32(DCM(ctx->opcode)); \
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gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
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cpu_env, ra, dcm); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_i32(dcm); \
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}
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#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr rt, rb; \
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TCGv_i32 u32_1, u32_2; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->nip - 4); \
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rt = gen_fprp_ptr(rD(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
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u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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tcg_temp_free_i32(u32_1); \
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tcg_temp_free_i32(u32_2); \
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}
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#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr rt, ra, rb; \
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TCGv_i32 i32; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->nip - 4); \
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rt = gen_fprp_ptr(rD(ctx->opcode)); \
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ra = gen_fprp_ptr(rA(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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i32 = tcg_const_i32(i32fld(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, ra, rb, i32); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_i32(i32); \
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}
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#define GEN_DFP_T_B_Rc(name) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr rt, rb; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->nip - 4); \
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rt = gen_fprp_ptr(rD(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, rb); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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}
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#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr rt, rs; \
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TCGv_i32 i32; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->nip - 4); \
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rt = gen_fprp_ptr(rD(ctx->opcode)); \
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rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
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i32 = tcg_const_i32(i32fld(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, rs, i32); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rs); \
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tcg_temp_free_i32(i32); \
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}
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GEN_DFP_T_A_B_Rc(dadd)
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GEN_DFP_T_A_B_Rc(daddq)
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GEN_DFP_T_A_B_Rc(dsub)
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GEN_DFP_T_A_B_Rc(dsubq)
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GEN_DFP_T_A_B_Rc(dmul)
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GEN_DFP_T_A_B_Rc(dmulq)
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GEN_DFP_T_A_B_Rc(ddiv)
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GEN_DFP_T_A_B_Rc(ddivq)
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GEN_DFP_BF_A_B(dcmpu)
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GEN_DFP_BF_A_B(dcmpuq)
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GEN_DFP_BF_A_B(dcmpo)
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GEN_DFP_BF_A_B(dcmpoq)
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GEN_DFP_BF_A_DCM(dtstdc)
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GEN_DFP_BF_A_DCM(dtstdcq)
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GEN_DFP_BF_A_DCM(dtstdg)
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GEN_DFP_BF_A_DCM(dtstdgq)
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GEN_DFP_BF_A_B(dtstex)
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GEN_DFP_BF_A_B(dtstexq)
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GEN_DFP_BF_A_B(dtstsf)
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GEN_DFP_BF_A_B(dtstsfq)
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GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
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GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
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GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
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GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
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GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
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GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
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GEN_DFP_T_B_Rc(dctdp)
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GEN_DFP_T_B_Rc(dctqpq)
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GEN_DFP_T_B_Rc(drsp)
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GEN_DFP_T_B_Rc(drdpq)
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GEN_DFP_T_B_Rc(dcffix)
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GEN_DFP_T_B_Rc(dcffixq)
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GEN_DFP_T_B_Rc(dctfix)
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GEN_DFP_T_B_Rc(dctfixq)
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GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
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GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
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GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
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GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
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GEN_DFP_T_B_Rc(dxex)
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GEN_DFP_T_B_Rc(dxexq)
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GEN_DFP_T_A_B_Rc(diex)
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GEN_DFP_T_A_B_Rc(diexq)
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GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
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GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
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GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
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GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
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#include "translate/dfp-impl.c"
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#include "translate/spe-impl.c"
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@ -8906,165 +8703,7 @@ GEN_XXSEL_ROW(0x1F)
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GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
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#undef GEN_DFP_T_A_B_Rc
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#undef GEN_DFP_BF_A_B
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#undef GEN_DFP_BF_A_DCM
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#undef GEN_DFP_T_B_U32_U32_Rc
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#undef GEN_DFP_T_A_B_I32_Rc
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#undef GEN_DFP_T_B_Rc
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#undef GEN_DFP_T_FPR_I32_Rc
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#define _GEN_DFP_LONG(name, op1, op2, mask) \
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GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
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#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
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GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
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GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
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#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
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GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
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GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
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GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
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GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
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#define _GEN_DFP_QUAD(name, op1, op2, mask) \
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GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
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#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
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GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
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GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
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#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
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GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
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GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
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GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
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GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
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#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
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_GEN_DFP_LONG(name, op1, op2, 0x00000000)
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#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
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_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
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#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
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_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
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#define GEN_DFP_T_B_Rc(name, op1, op2) \
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_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
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#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
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_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
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#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
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_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
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#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
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_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
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#define GEN_DFP_BF_A_B(name, op1, op2) \
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_GEN_DFP_LONG(name, op1, op2, 0x00000001)
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#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
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_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
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#define GEN_DFP_BF_A_Bp(name, op1, op2) \
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_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
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#define GEN_DFP_BF_A_DCM(name, op1, op2) \
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_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
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#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
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_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
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#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
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_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
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#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
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_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
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#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
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_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
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#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
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_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
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#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
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_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
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#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
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_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
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#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
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_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
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#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
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_GEN_DFP_LONG(name, op1, op2, 0x00070000)
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#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
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_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
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#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
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_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
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#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
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_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
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#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
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_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
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#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
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_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
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GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
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GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
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GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
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GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
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GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
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GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
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GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
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GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
|
||||
GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
|
||||
GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
|
||||
GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
|
||||
GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
|
||||
GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
|
||||
GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
|
||||
GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
|
||||
GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
|
||||
GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
|
||||
GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
|
||||
GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
|
||||
GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
|
||||
GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
|
||||
GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
|
||||
GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
|
||||
GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
|
||||
GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
|
||||
GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
|
||||
GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
|
||||
GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
|
||||
GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
|
||||
GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
|
||||
GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
|
||||
GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
|
||||
GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
|
||||
GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
|
||||
GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
|
||||
GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
|
||||
GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
|
||||
GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
|
||||
GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
|
||||
GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
|
||||
GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
|
||||
GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
|
||||
GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
|
||||
GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
|
||||
GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
|
||||
GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
|
||||
GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
|
||||
GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
|
||||
GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
|
||||
GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
|
||||
#include "translate/dfp-ops.c"
|
||||
|
||||
#include "translate/spe-ops.c"
|
||||
|
||||
|
|
|
@ -0,0 +1,212 @@
|
|||
/*** Decimal Floating Point ***/
|
||||
|
||||
static inline TCGv_ptr gen_fprp_ptr(int reg)
|
||||
{
|
||||
TCGv_ptr r = tcg_temp_new_ptr();
|
||||
tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
|
||||
return r;
|
||||
}
|
||||
|
||||
#define GEN_DFP_T_A_B_Rc(name) \
|
||||
static void gen_##name(DisasContext *ctx) \
|
||||
{ \
|
||||
TCGv_ptr rd, ra, rb; \
|
||||
if (unlikely(!ctx->fpu_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_FPU); \
|
||||
return; \
|
||||
} \
|
||||
gen_update_nip(ctx, ctx->nip - 4); \
|
||||
rd = gen_fprp_ptr(rD(ctx->opcode)); \
|
||||
ra = gen_fprp_ptr(rA(ctx->opcode)); \
|
||||
rb = gen_fprp_ptr(rB(ctx->opcode)); \
|
||||
gen_helper_##name(cpu_env, rd, ra, rb); \
|
||||
if (unlikely(Rc(ctx->opcode) != 0)) { \
|
||||
gen_set_cr1_from_fpscr(ctx); \
|
||||
} \
|
||||
tcg_temp_free_ptr(rd); \
|
||||
tcg_temp_free_ptr(ra); \
|
||||
tcg_temp_free_ptr(rb); \
|
||||
}
|
||||
|
||||
#define GEN_DFP_BF_A_B(name) \
|
||||
static void gen_##name(DisasContext *ctx) \
|
||||
{ \
|
||||
TCGv_ptr ra, rb; \
|
||||
if (unlikely(!ctx->fpu_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_FPU); \
|
||||
return; \
|
||||
} \
|
||||
gen_update_nip(ctx, ctx->nip - 4); \
|
||||
ra = gen_fprp_ptr(rA(ctx->opcode)); \
|
||||
rb = gen_fprp_ptr(rB(ctx->opcode)); \
|
||||
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
|
||||
cpu_env, ra, rb); \
|
||||
tcg_temp_free_ptr(ra); \
|
||||
tcg_temp_free_ptr(rb); \
|
||||
}
|
||||
|
||||
#define GEN_DFP_BF_A_DCM(name) \
|
||||
static void gen_##name(DisasContext *ctx) \
|
||||
{ \
|
||||
TCGv_ptr ra; \
|
||||
TCGv_i32 dcm; \
|
||||
if (unlikely(!ctx->fpu_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_FPU); \
|
||||
return; \
|
||||
} \
|
||||
gen_update_nip(ctx, ctx->nip - 4); \
|
||||
ra = gen_fprp_ptr(rA(ctx->opcode)); \
|
||||
dcm = tcg_const_i32(DCM(ctx->opcode)); \
|
||||
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
|
||||
cpu_env, ra, dcm); \
|
||||
tcg_temp_free_ptr(ra); \
|
||||
tcg_temp_free_i32(dcm); \
|
||||
}
|
||||
|
||||
#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
|
||||
static void gen_##name(DisasContext *ctx) \
|
||||
{ \
|
||||
TCGv_ptr rt, rb; \
|
||||
TCGv_i32 u32_1, u32_2; \
|
||||
if (unlikely(!ctx->fpu_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_FPU); \
|
||||
return; \
|
||||
} \
|
||||
gen_update_nip(ctx, ctx->nip - 4); \
|
||||
rt = gen_fprp_ptr(rD(ctx->opcode)); \
|
||||
rb = gen_fprp_ptr(rB(ctx->opcode)); \
|
||||
u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
|
||||
u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
|
||||
gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
|
||||
if (unlikely(Rc(ctx->opcode) != 0)) { \
|
||||
gen_set_cr1_from_fpscr(ctx); \
|
||||
} \
|
||||
tcg_temp_free_ptr(rt); \
|
||||
tcg_temp_free_ptr(rb); \
|
||||
tcg_temp_free_i32(u32_1); \
|
||||
tcg_temp_free_i32(u32_2); \
|
||||
}
|
||||
|
||||
#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
|
||||
static void gen_##name(DisasContext *ctx) \
|
||||
{ \
|
||||
TCGv_ptr rt, ra, rb; \
|
||||
TCGv_i32 i32; \
|
||||
if (unlikely(!ctx->fpu_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_FPU); \
|
||||
return; \
|
||||
} \
|
||||
gen_update_nip(ctx, ctx->nip - 4); \
|
||||
rt = gen_fprp_ptr(rD(ctx->opcode)); \
|
||||
ra = gen_fprp_ptr(rA(ctx->opcode)); \
|
||||
rb = gen_fprp_ptr(rB(ctx->opcode)); \
|
||||
i32 = tcg_const_i32(i32fld(ctx->opcode)); \
|
||||
gen_helper_##name(cpu_env, rt, ra, rb, i32); \
|
||||
if (unlikely(Rc(ctx->opcode) != 0)) { \
|
||||
gen_set_cr1_from_fpscr(ctx); \
|
||||
} \
|
||||
tcg_temp_free_ptr(rt); \
|
||||
tcg_temp_free_ptr(rb); \
|
||||
tcg_temp_free_ptr(ra); \
|
||||
tcg_temp_free_i32(i32); \
|
||||
}
|
||||
|
||||
#define GEN_DFP_T_B_Rc(name) \
|
||||
static void gen_##name(DisasContext *ctx) \
|
||||
{ \
|
||||
TCGv_ptr rt, rb; \
|
||||
if (unlikely(!ctx->fpu_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_FPU); \
|
||||
return; \
|
||||
} \
|
||||
gen_update_nip(ctx, ctx->nip - 4); \
|
||||
rt = gen_fprp_ptr(rD(ctx->opcode)); \
|
||||
rb = gen_fprp_ptr(rB(ctx->opcode)); \
|
||||
gen_helper_##name(cpu_env, rt, rb); \
|
||||
if (unlikely(Rc(ctx->opcode) != 0)) { \
|
||||
gen_set_cr1_from_fpscr(ctx); \
|
||||
} \
|
||||
tcg_temp_free_ptr(rt); \
|
||||
tcg_temp_free_ptr(rb); \
|
||||
}
|
||||
|
||||
#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
|
||||
static void gen_##name(DisasContext *ctx) \
|
||||
{ \
|
||||
TCGv_ptr rt, rs; \
|
||||
TCGv_i32 i32; \
|
||||
if (unlikely(!ctx->fpu_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_FPU); \
|
||||
return; \
|
||||
} \
|
||||
gen_update_nip(ctx, ctx->nip - 4); \
|
||||
rt = gen_fprp_ptr(rD(ctx->opcode)); \
|
||||
rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
|
||||
i32 = tcg_const_i32(i32fld(ctx->opcode)); \
|
||||
gen_helper_##name(cpu_env, rt, rs, i32); \
|
||||
if (unlikely(Rc(ctx->opcode) != 0)) { \
|
||||
gen_set_cr1_from_fpscr(ctx); \
|
||||
} \
|
||||
tcg_temp_free_ptr(rt); \
|
||||
tcg_temp_free_ptr(rs); \
|
||||
tcg_temp_free_i32(i32); \
|
||||
}
|
||||
|
||||
GEN_DFP_T_A_B_Rc(dadd)
|
||||
GEN_DFP_T_A_B_Rc(daddq)
|
||||
GEN_DFP_T_A_B_Rc(dsub)
|
||||
GEN_DFP_T_A_B_Rc(dsubq)
|
||||
GEN_DFP_T_A_B_Rc(dmul)
|
||||
GEN_DFP_T_A_B_Rc(dmulq)
|
||||
GEN_DFP_T_A_B_Rc(ddiv)
|
||||
GEN_DFP_T_A_B_Rc(ddivq)
|
||||
GEN_DFP_BF_A_B(dcmpu)
|
||||
GEN_DFP_BF_A_B(dcmpuq)
|
||||
GEN_DFP_BF_A_B(dcmpo)
|
||||
GEN_DFP_BF_A_B(dcmpoq)
|
||||
GEN_DFP_BF_A_DCM(dtstdc)
|
||||
GEN_DFP_BF_A_DCM(dtstdcq)
|
||||
GEN_DFP_BF_A_DCM(dtstdg)
|
||||
GEN_DFP_BF_A_DCM(dtstdgq)
|
||||
GEN_DFP_BF_A_B(dtstex)
|
||||
GEN_DFP_BF_A_B(dtstexq)
|
||||
GEN_DFP_BF_A_B(dtstsf)
|
||||
GEN_DFP_BF_A_B(dtstsfq)
|
||||
GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
|
||||
GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
|
||||
GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
|
||||
GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
|
||||
GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
|
||||
GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
|
||||
GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
|
||||
GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
|
||||
GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
|
||||
GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
|
||||
GEN_DFP_T_B_Rc(dctdp)
|
||||
GEN_DFP_T_B_Rc(dctqpq)
|
||||
GEN_DFP_T_B_Rc(drsp)
|
||||
GEN_DFP_T_B_Rc(drdpq)
|
||||
GEN_DFP_T_B_Rc(dcffix)
|
||||
GEN_DFP_T_B_Rc(dcffixq)
|
||||
GEN_DFP_T_B_Rc(dctfix)
|
||||
GEN_DFP_T_B_Rc(dctfixq)
|
||||
GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
|
||||
GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
|
||||
GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
|
||||
GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
|
||||
GEN_DFP_T_B_Rc(dxex)
|
||||
GEN_DFP_T_B_Rc(dxexq)
|
||||
GEN_DFP_T_A_B_Rc(diex)
|
||||
GEN_DFP_T_A_B_Rc(diexq)
|
||||
GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
|
||||
GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
|
||||
GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
|
||||
GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
|
||||
|
||||
#undef GEN_DFP_T_A_B_Rc
|
||||
#undef GEN_DFP_BF_A_B
|
||||
#undef GEN_DFP_BF_A_DCM
|
||||
#undef GEN_DFP_T_B_U32_U32_Rc
|
||||
#undef GEN_DFP_T_A_B_I32_Rc
|
||||
#undef GEN_DFP_T_B_Rc
|
||||
#undef GEN_DFP_T_FPR_I32_Rc
|
|
@ -0,0 +1,151 @@
|
|||
#define _GEN_DFP_LONG(name, op1, op2, mask) \
|
||||
GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
|
||||
|
||||
#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
|
||||
GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
|
||||
GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
|
||||
|
||||
#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
|
||||
GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
|
||||
GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
|
||||
GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
|
||||
GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
|
||||
|
||||
#define _GEN_DFP_QUAD(name, op1, op2, mask) \
|
||||
GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
|
||||
|
||||
#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
|
||||
GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
|
||||
GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
|
||||
|
||||
#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
|
||||
GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
|
||||
GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
|
||||
GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
|
||||
GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
|
||||
|
||||
#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
|
||||
_GEN_DFP_LONG(name, op1, op2, 0x00000000)
|
||||
|
||||
#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
|
||||
|
||||
#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
|
||||
|
||||
#define GEN_DFP_T_B_Rc(name, op1, op2) \
|
||||
_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
|
||||
|
||||
#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
|
||||
|
||||
#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
|
||||
|
||||
#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
|
||||
|
||||
#define GEN_DFP_BF_A_B(name, op1, op2) \
|
||||
_GEN_DFP_LONG(name, op1, op2, 0x00000001)
|
||||
|
||||
#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
|
||||
_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
|
||||
|
||||
#define GEN_DFP_BF_A_Bp(name, op1, op2) \
|
||||
_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
|
||||
|
||||
#define GEN_DFP_BF_A_DCM(name, op1, op2) \
|
||||
_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
|
||||
|
||||
#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
|
||||
_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
|
||||
|
||||
#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
|
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_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
|
||||
|
||||
#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
|
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_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
|
||||
|
||||
#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
|
||||
|
||||
#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
|
||||
_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
|
||||
|
||||
#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
|
||||
|
||||
#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
|
||||
_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
|
||||
|
||||
#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
|
||||
|
||||
#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
|
||||
_GEN_DFP_LONG(name, op1, op2, 0x00070000)
|
||||
|
||||
#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
|
||||
|
||||
#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
|
||||
_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
|
||||
|
||||
#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
|
||||
|
||||
#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
|
||||
_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
|
||||
|
||||
#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
|
||||
_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
|
||||
|
||||
GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
|
||||
GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
|
||||
GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
|
||||
GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
|
||||
GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
|
||||
GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
|
||||
GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
|
||||
GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
|
||||
GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
|
||||
GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
|
||||
GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
|
||||
GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
|
||||
GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
|
||||
GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
|
||||
GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
|
||||
GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
|
||||
GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
|
||||
GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
|
||||
GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
|
||||
GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
|
||||
GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
|
||||
GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
|
||||
GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
|
||||
GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
|
||||
GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
|
||||
GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
|
||||
GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
|
||||
GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
|
||||
GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
|
||||
GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
|
||||
GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
|
||||
GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
|
||||
GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
|
||||
GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
|
||||
GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
|
||||
GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
|
||||
GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
|
||||
GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
|
||||
GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
|
||||
GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
|
||||
GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
|
||||
GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
|
||||
GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
|
||||
GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
|
||||
GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
|
||||
GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
|
||||
GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
|
||||
GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
|
||||
GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
|
||||
GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
|
Loading…
Reference in New Issue