From 8b5ff57115e60589d772efeaa0c061ad6701e340 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 21 Aug 2012 14:33:36 -0700 Subject: [PATCH] target-s390: Convert LOAD PSW Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 2 ++ target-s390x/translate.c | 41 +++++++++++++++++++------------------- 2 files changed, 23 insertions(+), 20 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 45c36c1607..b0bee9baf0 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -379,6 +379,8 @@ D(0xa701, TMLL, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 0) #ifndef CONFIG_USER_ONLY +/* LOAD PSW */ + C(0x8200, LPSW, S, Z, 0, a2, 0, 0, lpsw, 0) /* SET ADDRESSING MODE */ /* We only do 64-bit, so accept this as a no-op. Let SAM24 and SAM31 signal illegal instruction. */ diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 246d0f0a9a..cbfcf41427 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2356,26 +2356,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) switch (opc) { #ifndef CONFIG_USER_ONLY - case 0x82: /* LPSW D2(B2) [S] */ - /* Load PSW */ - check_privileged(s); - insn = ld_code4(env, s->pc); - decode_rs(s, insn, &r1, &r3, &b2, &d2); - tmp = get_address(s, 0, b2, d2); - tmp2 = tcg_temp_new_i64(); - tmp3 = tcg_temp_new_i64(); - tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); - tcg_gen_addi_i64(tmp, tmp, 4); - tcg_gen_qemu_ld32u(tmp3, tmp, get_mem_index(s)); - /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */ - tcg_gen_shli_i64(tmp2, tmp2, 32); - gen_helper_load_psw(cpu_env, tmp2, tmp3); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - tcg_temp_free_i64(tmp3); - /* we need to keep cc_op intact */ - s->is_jmp = DISAS_JUMP; - break; case 0x83: /* DIAG R1,R3,D2 [RS] */ /* Diagnose call (KVM hypercall) */ check_privileged(s); @@ -3511,6 +3491,27 @@ static ExitStatus op_ld64(DisasContext *s, DisasOps *o) return NO_EXIT; } +#ifndef CONFIG_USER_ONLY +static ExitStatus op_lpsw(DisasContext *s, DisasOps *o) +{ + TCGv_i64 t1, t2; + + check_privileged(s); + + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); + tcg_gen_addi_i64(o->in2, o->in2, 4); + tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s)); + /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */ + tcg_gen_shli_i64(t1, t1, 32); + gen_helper_load_psw(cpu_env, t1, t2); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + return EXIT_NORETURN; +} +#endif + static ExitStatus op_mov2(DisasContext *s, DisasOps *o) { o->out = o->in2;