diff --git a/tests/tcg/xtensa/test_interrupt.S b/tests/tcg/xtensa/test_interrupt.S index 334ddab287..876683518e 100644 --- a/tests/tcg/xtensa/test_interrupt.S +++ b/tests/tcg/xtensa/test_interrupt.S @@ -1,5 +1,7 @@ #include "macros.inc" +#define LSBIT(v) ((v) ^ ((v) & ((v) - 1))) + test_suite interrupt .macro clear_interrupts @@ -46,14 +48,17 @@ test soft_disabled set_vector kernel, 1f clear_interrupts - movi a2, 0x80 + movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE) wsr a2, intset esync rsr a3, interrupt + movi a4, ~XCHAL_INTTYPE_MASK_TIMER + and a3, a3, a4 assert eq, a2, a3 wsr a2, intclear esync rsr a3, interrupt + and a3, a3, a4 assert eqi, a3, 0 j 2f 1: @@ -65,10 +70,12 @@ test soft_intenable set_vector kernel, 1f clear_interrupts - movi a2, 0x80 + movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE) wsr a2, intset esync rsr a3, interrupt + movi a4, ~XCHAL_INTTYPE_MASK_TIMER + and a3, a3, a4 assert eq, a2, a3 rsil a3, 0 wsr a2, intenable @@ -82,10 +89,12 @@ test soft_rsil set_vector kernel, 1f clear_interrupts - movi a2, 0x80 + movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE) wsr a2, intset esync rsr a3, interrupt + movi a4, ~XCHAL_INTTYPE_MASK_TIMER + and a3, a3, a4 assert eq, a2, a3 wsr a2, intenable rsil a3, 0 @@ -99,10 +108,12 @@ test soft_waiti set_vector kernel, 1f clear_interrupts - movi a2, 0x80 + movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE) wsr a2, intset esync rsr a3, interrupt + movi a4, ~XCHAL_INTTYPE_MASK_TIMER + and a3, a3, a4 assert eq, a2, a3 wsr a2, intenable waiti 0 @@ -116,10 +127,12 @@ test soft_user set_vector user, 2f clear_interrupts - movi a2, 0x80 + movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE) wsr a2, intset esync rsr a3, interrupt + movi a4, ~XCHAL_INTTYPE_MASK_TIMER + and a3, a3, a4 assert eq, a2, a3 wsr a2, intenable @@ -139,7 +152,7 @@ test soft_priority set_vector level3, 2f clear_interrupts - movi a2, 0x880 + movi a2, XCHAL_INTTYPE_MASK_SOFTWARE wsr a2, intenable rsil a3, 0 esync @@ -161,7 +174,7 @@ test eps_epc_rfi clear_interrupts reset_ps - movi a2, 0x880 + movi a2, XCHAL_INTTYPE_MASK_SOFTWARE wsr a2, intenable rsil a3, 0 rsr a3, ps