vitalif
/
mirror_qemu
mirror of https://github.com/proxmox/mirror_qemu
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/mips/cp0_timer: Document TIMER_PERIOD origin 

TIMER_PERIOD value of '10 ns' can be explained looking at
commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz
and CP0 default count rate is half the frequency of the
CPU. Document that.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-8-f4bug@amsat.org>
master
Philippe Mathieu-Daudé 2020-10-12 11:57:50 +02:00
parent 62f8f2603d
commit 8dadffc017
1 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
target/mips/cp0_timer.c
View File

@ -27,7 +27,17 @@
#include "sysemu/kvm.h"
#include "internal.h"
#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
/*
* Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz
* and a CP0 timer running at half the clock of the CPU (cp0_count_rate = 2).
*
* TIMER_FREQ_HZ = CPU_FREQ_HZ / CP0_COUNT_RATE = 200 MHz / 2 = 100 MHz
*
* TIMER_PERIOD_NS = 1 / TIMER_FREQ_HZ = 10 ns
*/
#define CPU_FREQ_HZ_DEFAULT 200000000
#define CP0_COUNT_RATE_DEFAULT 2
#define TIMER_PERIOD 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) */
/* MIPS R4K timer */
static void cpu_mips_timer_update(CPUMIPSState *env)