diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index d6d0c2dc70..e6c1098e47 100644
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -261,6 +261,16 @@ static void dfp_check_for_VXISI_subtract(struct PPC_DFP *dfp)
     dfp_check_for_VXISI(dfp, 1);
 }
 
+static void dfp_check_for_VXIMZ(struct PPC_DFP *dfp)
+{
+    if (dfp->context.status & DEC_Invalid_operation) {
+        if ((decNumberIsInfinite(&dfp->a) && decNumberIsZero(&dfp->b)) ||
+            (decNumberIsInfinite(&dfp->b) && decNumberIsZero(&dfp->a))) {
+            dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXIMZ, FP_VE);
+        }
+    }
+}
+
 #define DFP_HELPER_TAB(op, dnop, postprocs, size)                              \
 void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a, uint64_t *b)      \
 {                                                                              \
@@ -302,3 +312,16 @@ static void SUB_PPs(struct PPC_DFP *dfp)
 
 DFP_HELPER_TAB(dsub, decNumberSubtract, SUB_PPs, 64)
 DFP_HELPER_TAB(dsubq, decNumberSubtract, SUB_PPs, 128)
+
+static void MUL_PPs(struct PPC_DFP *dfp)
+{
+    dfp_set_FPRF_from_FRT(dfp);
+    dfp_check_for_OX(dfp);
+    dfp_check_for_UX(dfp);
+    dfp_check_for_XX(dfp);
+    dfp_check_for_VXSNAN(dfp);
+    dfp_check_for_VXIMZ(dfp);
+}
+
+DFP_HELPER_TAB(dmul, decNumberMultiply, MUL_PPs, 64)
+DFP_HELPER_TAB(dmulq, decNumberMultiply, MUL_PPs, 128)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index d560e532d9..ac23556aa4 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -620,3 +620,5 @@ DEF_HELPER_4(dadd, void, env, fprp, fprp, fprp)
 DEF_HELPER_4(daddq, void, env, fprp, fprp, fprp)
 DEF_HELPER_4(dsub, void, env, fprp, fprp, fprp)
 DEF_HELPER_4(dsubq, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(dmul, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(dmulq, void, env, fprp, fprp, fprp)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e1075d5a66..3f8de17ce0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -8360,6 +8360,8 @@ GEN_DFP_T_A_B_Rc(dadd)
 GEN_DFP_T_A_B_Rc(daddq)
 GEN_DFP_T_A_B_Rc(dsub)
 GEN_DFP_T_A_B_Rc(dsubq)
+GEN_DFP_T_A_B_Rc(dmul)
+GEN_DFP_T_A_B_Rc(dmulq)
 /***                           SPE extension                               ***/
 /* Register moves */
 
@@ -11291,6 +11293,8 @@ GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
+GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
+GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
 #undef GEN_SPE
 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
     GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)