mirror of https://github.com/proxmox/mirror_qemu
ppc/xics: rename 'ICPState *' variables to 'icp'
'ICPState *' variables are currently named 'ss'. This is confusing, so let's give them an appropriate name: 'icp'. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>master
Cédric Le Goater
David Gibson
parent
6449da4545
commit
8e4fba203e
154
hw/intc/xics.c
154
hw/intc/xics.c
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@ -52,38 +52,38 @@ int xics_get_cpu_index_by_dt_id(int cpu_dt_id)
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void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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ICPState *ss = xics_icp_get(xi, cs->cpu_index);
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ICPState *icp = xics_icp_get(xi, cs->cpu_index);
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assert(ss);
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assert(cs == ss->cs);
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assert(icp);
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assert(cs == icp->cs);
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ss->output = NULL;
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ss->cs = NULL;
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icp->output = NULL;
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icp->cs = NULL;
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}
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void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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ICPState *ss = xics_icp_get(xi, cs->cpu_index);
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ICPState *icp = xics_icp_get(xi, cs->cpu_index);
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ICPStateClass *icpc;
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assert(ss);
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assert(icp);
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ss->cs = cs;
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icp->cs = cs;
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icpc = ICP_GET_CLASS(ss);
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icpc = ICP_GET_CLASS(icp);
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if (icpc->cpu_setup) {
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icpc->cpu_setup(ss, cpu);
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icpc->cpu_setup(icp, cpu);
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}
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switch (PPC_INPUT(env)) {
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case PPC_FLAGS_INPUT_POWER7:
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ss->output = env->irq_inputs[POWER7_INPUT_INT];
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icp->output = env->irq_inputs[POWER7_INPUT_INT];
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break;
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case PPC_FLAGS_INPUT_970:
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ss->output = env->irq_inputs[PPC970_INPUT_INT];
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icp->output = env->irq_inputs[PPC970_INPUT_INT];
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break;
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default:
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@ -137,8 +137,8 @@ void ics_pic_print_info(ICSState *ics, Monitor *mon)
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#define XISR_MASK 0x00ffffff
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#define CPPR_MASK 0xff000000
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#define XISR(ss) (((ss)->xirr) & XISR_MASK)
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#define CPPR(ss) (((ss)->xirr) >> 24)
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#define XISR(icp) (((icp)->xirr) & XISR_MASK)
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#define CPPR(icp) (((icp)->xirr) >> 24)
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static void ics_reject(ICSState *ics, uint32_t nr)
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{
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@ -167,152 +167,152 @@ static void ics_eoi(ICSState *ics, int nr)
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}
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}
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static void icp_check_ipi(ICPState *ss)
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static void icp_check_ipi(ICPState *icp)
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{
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if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
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if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
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return;
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}
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trace_xics_icp_check_ipi(ss->cs->cpu_index, ss->mfrr);
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trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
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if (XISR(ss) && ss->xirr_owner) {
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ics_reject(ss->xirr_owner, XISR(ss));
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if (XISR(icp) && icp->xirr_owner) {
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ics_reject(icp->xirr_owner, XISR(icp));
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}
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ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
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ss->pending_priority = ss->mfrr;
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ss->xirr_owner = NULL;
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qemu_irq_raise(ss->output);
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icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
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icp->pending_priority = icp->mfrr;
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icp->xirr_owner = NULL;
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qemu_irq_raise(icp->output);
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}
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void icp_resend(ICPState *ss)
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void icp_resend(ICPState *icp)
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{
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XICSFabric *xi = ss->xics;
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XICSFabric *xi = icp->xics;
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XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
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if (ss->mfrr < CPPR(ss)) {
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icp_check_ipi(ss);
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if (icp->mfrr < CPPR(icp)) {
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icp_check_ipi(icp);
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}
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xic->ics_resend(xi);
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}
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void icp_set_cppr(ICPState *ss, uint8_t cppr)
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void icp_set_cppr(ICPState *icp, uint8_t cppr)
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{
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uint8_t old_cppr;
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uint32_t old_xisr;
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old_cppr = CPPR(ss);
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ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);
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old_cppr = CPPR(icp);
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icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
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if (cppr < old_cppr) {
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if (XISR(ss) && (cppr <= ss->pending_priority)) {
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old_xisr = XISR(ss);
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ss->xirr &= ~XISR_MASK; /* Clear XISR */
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ss->pending_priority = 0xff;
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qemu_irq_lower(ss->output);
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if (ss->xirr_owner) {
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ics_reject(ss->xirr_owner, old_xisr);
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ss->xirr_owner = NULL;
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if (XISR(icp) && (cppr <= icp->pending_priority)) {
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old_xisr = XISR(icp);
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icp->xirr &= ~XISR_MASK; /* Clear XISR */
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icp->pending_priority = 0xff;
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qemu_irq_lower(icp->output);
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if (icp->xirr_owner) {
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ics_reject(icp->xirr_owner, old_xisr);
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icp->xirr_owner = NULL;
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}
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}
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} else {
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if (!XISR(ss)) {
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icp_resend(ss);
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if (!XISR(icp)) {
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icp_resend(icp);
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}
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}
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}
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void icp_set_mfrr(ICPState *ss, uint8_t mfrr)
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void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
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{
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ss->mfrr = mfrr;
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if (mfrr < CPPR(ss)) {
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icp_check_ipi(ss);
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icp->mfrr = mfrr;
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if (mfrr < CPPR(icp)) {
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icp_check_ipi(icp);
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}
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}
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uint32_t icp_accept(ICPState *ss)
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uint32_t icp_accept(ICPState *icp)
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{
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uint32_t xirr = ss->xirr;
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uint32_t xirr = icp->xirr;
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qemu_irq_lower(ss->output);
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ss->xirr = ss->pending_priority << 24;
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ss->pending_priority = 0xff;
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ss->xirr_owner = NULL;
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qemu_irq_lower(icp->output);
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icp->xirr = icp->pending_priority << 24;
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icp->pending_priority = 0xff;
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icp->xirr_owner = NULL;
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trace_xics_icp_accept(xirr, ss->xirr);
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trace_xics_icp_accept(xirr, icp->xirr);
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return xirr;
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}
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uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr)
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uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
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{
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if (mfrr) {
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*mfrr = ss->mfrr;
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*mfrr = icp->mfrr;
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}
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return ss->xirr;
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return icp->xirr;
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}
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void icp_eoi(ICPState *ss, uint32_t xirr)
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void icp_eoi(ICPState *icp, uint32_t xirr)
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{
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XICSFabric *xi = ss->xics;
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XICSFabric *xi = icp->xics;
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XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
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ICSState *ics;
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uint32_t irq;
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/* Send EOI -> ICS */
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ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
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trace_xics_icp_eoi(ss->cs->cpu_index, xirr, ss->xirr);
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icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
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trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
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irq = xirr & XISR_MASK;
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ics = xic->ics_get(xi, irq);
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if (ics) {
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ics_eoi(ics, irq);
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}
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if (!XISR(ss)) {
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icp_resend(ss);
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if (!XISR(icp)) {
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icp_resend(icp);
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}
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}
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static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
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{
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ICPState *ss = xics_icp_get(ics->xics, server);
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ICPState *icp = xics_icp_get(ics->xics, server);
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trace_xics_icp_irq(server, nr, priority);
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if ((priority >= CPPR(ss))
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|| (XISR(ss) && (ss->pending_priority <= priority))) {
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if ((priority >= CPPR(icp))
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|| (XISR(icp) && (icp->pending_priority <= priority))) {
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ics_reject(ics, nr);
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} else {
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if (XISR(ss) && ss->xirr_owner) {
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ics_reject(ss->xirr_owner, XISR(ss));
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ss->xirr_owner = NULL;
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if (XISR(icp) && icp->xirr_owner) {
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ics_reject(icp->xirr_owner, XISR(icp));
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icp->xirr_owner = NULL;
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}
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ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
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ss->xirr_owner = ics;
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ss->pending_priority = priority;
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trace_xics_icp_raise(ss->xirr, ss->pending_priority);
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qemu_irq_raise(ss->output);
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icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
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icp->xirr_owner = ics;
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icp->pending_priority = priority;
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trace_xics_icp_raise(icp->xirr, icp->pending_priority);
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qemu_irq_raise(icp->output);
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}
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}
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static void icp_dispatch_pre_save(void *opaque)
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{
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ICPState *ss = opaque;
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ICPStateClass *info = ICP_GET_CLASS(ss);
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ICPState *icp = opaque;
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ICPStateClass *info = ICP_GET_CLASS(icp);
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if (info->pre_save) {
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info->pre_save(ss);
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info->pre_save(icp);
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}
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}
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static int icp_dispatch_post_load(void *opaque, int version_id)
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{
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ICPState *ss = opaque;
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ICPStateClass *info = ICP_GET_CLASS(ss);
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ICPState *icp = opaque;
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ICPStateClass *info = ICP_GET_CLASS(icp);
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if (info->post_load) {
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return info->post_load(ss, version_id);
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return info->post_load(icp, version_id);
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}
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return 0;
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@ -45,7 +45,7 @@ static int kernel_xics_fd = -1;
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/*
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* ICP-KVM
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*/
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static void icp_get_kvm_state(ICPState *ss)
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static void icp_get_kvm_state(ICPState *icp)
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{
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uint64_t state;
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struct kvm_one_reg reg = {
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@ -55,25 +55,25 @@ static void icp_get_kvm_state(ICPState *ss)
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int ret;
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/* ICP for this CPU thread is not in use, exiting */
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if (!ss->cs) {
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if (!icp->cs) {
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return;
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}
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ret = kvm_vcpu_ioctl(ss->cs, KVM_GET_ONE_REG, ®);
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ret = kvm_vcpu_ioctl(icp->cs, KVM_GET_ONE_REG, ®);
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if (ret != 0) {
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error_report("Unable to retrieve KVM interrupt controller state"
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" for CPU %ld: %s", kvm_arch_vcpu_id(ss->cs), strerror(errno));
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" for CPU %ld: %s", kvm_arch_vcpu_id(icp->cs), strerror(errno));
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exit(1);
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}
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ss->xirr = state >> KVM_REG_PPC_ICP_XISR_SHIFT;
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ss->mfrr = (state >> KVM_REG_PPC_ICP_MFRR_SHIFT)
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icp->xirr = state >> KVM_REG_PPC_ICP_XISR_SHIFT;
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icp->mfrr = (state >> KVM_REG_PPC_ICP_MFRR_SHIFT)
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& KVM_REG_PPC_ICP_MFRR_MASK;
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ss->pending_priority = (state >> KVM_REG_PPC_ICP_PPRI_SHIFT)
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icp->pending_priority = (state >> KVM_REG_PPC_ICP_PPRI_SHIFT)
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& KVM_REG_PPC_ICP_PPRI_MASK;
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}
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static int icp_set_kvm_state(ICPState *ss, int version_id)
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static int icp_set_kvm_state(ICPState *icp, int version_id)
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{
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uint64_t state;
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struct kvm_one_reg reg = {
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@ -83,18 +83,18 @@ static int icp_set_kvm_state(ICPState *ss, int version_id)
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int ret;
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/* ICP for this CPU thread is not in use, exiting */
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if (!ss->cs) {
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if (!icp->cs) {
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return 0;
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}
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state = ((uint64_t)ss->xirr << KVM_REG_PPC_ICP_XISR_SHIFT)
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| ((uint64_t)ss->mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT)
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| ((uint64_t)ss->pending_priority << KVM_REG_PPC_ICP_PPRI_SHIFT);
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state = ((uint64_t)icp->xirr << KVM_REG_PPC_ICP_XISR_SHIFT)
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| ((uint64_t)icp->mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT)
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| ((uint64_t)icp->pending_priority << KVM_REG_PPC_ICP_PPRI_SHIFT);
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ret = kvm_vcpu_ioctl(ss->cs, KVM_SET_ONE_REG, ®);
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ret = kvm_vcpu_ioctl(icp->cs, KVM_SET_ONE_REG, ®);
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if (ret != 0) {
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error_report("Unable to restore KVM interrupt controller state (0x%"
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PRIx64 ") for CPU %ld: %s", state, kvm_arch_vcpu_id(ss->cs),
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PRIx64 ") for CPU %ld: %s", state, kvm_arch_vcpu_id(icp->cs),
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strerror(errno));
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return ret;
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}
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@ -118,7 +118,7 @@ static void icp_kvm_reset(DeviceState *dev)
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icp_set_kvm_state(icp, 1);
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}
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static void icp_kvm_cpu_setup(ICPState *ss, PowerPCCPU *cpu)
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static void icp_kvm_cpu_setup(ICPState *icp, PowerPCCPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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int ret;
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@ -132,7 +132,7 @@ static void icp_kvm_cpu_setup(ICPState *ss, PowerPCCPU *cpu)
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* which was hot-removed earlier we don't have to renable
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* KVM_CAP_IRQ_XICS capability again.
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*/
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if (ss->cap_irq_xics_enabled) {
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if (icp->cap_irq_xics_enabled) {
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return;
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}
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@ -143,7 +143,7 @@ static void icp_kvm_cpu_setup(ICPState *ss, PowerPCCPU *cpu)
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kvm_arch_vcpu_id(cs), strerror(errno));
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exit(1);
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}
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ss->cap_irq_xics_enabled = true;
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icp->cap_irq_xics_enabled = true;
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}
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static void icp_kvm_class_init(ObjectClass *klass, void *data)
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