mirror of https://github.com/proxmox/mirror_qemu
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array. Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] array for them. Add all these properties in riscv_cpu_add_user_properties() as it is already being done today. 'mmu' and 'pmp' aren't really extensions in the usual way we think about RISC-V extensions. These are closer to CPU features/options, so move both to riscv_cpu_options[] too. In the near future we'll need to match all extensions with all entries in isa_edata_arr[], and so it happens that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv spec version restriction). This further emphasizes the point that these are more a CPU option than an extension. No functional changes made. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230912132423.268494-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>master
parent
a51e5124a6
commit
8ea3fceff4
|
@ -1806,7 +1806,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
|
|||
|
||||
static Property riscv_cpu_extensions[] = {
|
||||
/* Defaults for standard extensions */
|
||||
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
|
||||
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
|
||||
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
|
||||
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
|
||||
|
@ -1819,15 +1818,8 @@ static Property riscv_cpu_extensions[] = {
|
|||
DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
|
||||
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
|
||||
DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
|
||||
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
|
||||
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
|
||||
DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
|
||||
|
||||
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
|
||||
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
|
||||
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
|
||||
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
|
||||
|
||||
DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
|
||||
DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
|
||||
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
|
||||
|
@ -1858,9 +1850,7 @@ static Property riscv_cpu_extensions[] = {
|
|||
DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
|
||||
|
||||
DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
|
||||
DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
|
||||
DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
|
||||
DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
|
||||
|
||||
DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
|
||||
|
||||
|
@ -1914,6 +1904,21 @@ static Property riscv_cpu_extensions[] = {
|
|||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static Property riscv_cpu_options[] = {
|
||||
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
|
||||
|
||||
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
|
||||
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
|
||||
|
||||
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
|
||||
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
|
||||
|
||||
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
|
||||
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
|
||||
|
||||
DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
|
||||
DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
|
||||
};
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
|
||||
|
@ -1982,6 +1987,14 @@ static void riscv_cpu_add_user_properties(Object *obj)
|
|||
#endif
|
||||
qdev_property_add_static(dev, prop);
|
||||
}
|
||||
|
||||
for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
|
||||
/* Check if KVM created the property already */
|
||||
if (object_property_find(obj, riscv_cpu_options[i].name)) {
|
||||
continue;
|
||||
}
|
||||
qdev_property_add_static(dev, &riscv_cpu_options[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static Property riscv_cpu_properties[] = {
|
||||
|
|
Loading…
Reference in New Issue