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target/mips: Clean up handling of CP0 register 6 

Clean up handling of CP0 register 6.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-8-git-send-email-aleksandar.markovic@rt-rk.com>
master
Aleksandar Markovic 2019-08-28 18:26:31 +02:00
parent a1e76353e3
commit 9023594b40
2 changed files with 34 additions and 28 deletions
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6
target/mips/cpu.h
View File

@ -321,6 +321,12 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG05__PWSIZE 7 #define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */ /* CP0 Register 06 */
#define CP0_REG06__WIRED 0 #define CP0_REG06__WIRED 0
#define CP0_REG06__SRSCONF0 1
#define CP0_REG06__SRSCONF1 2
#define CP0_REG06__SRSCONF2 3
#define CP0_REG06__SRSCONF3 4
#define CP0_REG06__SRSCONF4 5
#define CP0_REG06__PWCTL 6
/* CP0 Register 07 */ /* CP0 Register 07 */
#define CP0_REG07__HWRENA 0 #define CP0_REG07__HWRENA 0
/* CP0 Register 08 */ /* CP0 Register 08 */

56
target/mips/translate.c
View File

@ -7046,36 +7046,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_06: case CP0_REGISTER_06:
switch (sel) { switch (sel) {
case 0: case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired"; register_name = "Wired";
break; break;
case 1: case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0"; register_name = "SRSConf0";
break; break;
case 2: case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1"; register_name = "SRSConf1";
break; break;
case 3: case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2"; register_name = "SRSConf2";
break; break;
case 4: case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3"; register_name = "SRSConf3";
break; break;
case 5: case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4"; register_name = "SRSConf4";
break; break;
case 6: case CP0_REG06__PWCTL:
check_pw(ctx); check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl"; register_name = "PWCtl";
@ -7778,36 +7778,36 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_06: case CP0_REGISTER_06:
switch (sel) { switch (sel) {
case 0: case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg); gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired"; register_name = "Wired";
break; break;
case 1: case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg); gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0"; register_name = "SRSConf0";
break; break;
case 2: case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg); gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1"; register_name = "SRSConf1";
break; break;
case 3: case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg); gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2"; register_name = "SRSConf2";
break; break;
case 4: case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg); gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3"; register_name = "SRSConf3";
break; break;
case 5: case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg); gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4"; register_name = "SRSConf4";
break; break;
case 6: case CP0_REG06__PWCTL:
check_pw(ctx); check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg); gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl"; register_name = "PWCtl";
@ -8523,36 +8523,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_06: case CP0_REGISTER_06:
switch (sel) { switch (sel) {
case 0: case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired"; register_name = "Wired";
break; break;
case 1: case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0"; register_name = "SRSConf0";
break; break;
case 2: case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1"; register_name = "SRSConf1";
break; break;
case 3: case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2"; register_name = "SRSConf2";
break; break;
case 4: case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3"; register_name = "SRSConf3";
break; break;
case 5: case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4"; register_name = "SRSConf4";
break; break;
case 6: case CP0_REG06__PWCTL:
check_pw(ctx); check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl"; register_name = "PWCtl";
@ -9237,36 +9237,36 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_06: case CP0_REGISTER_06:
switch (sel) { switch (sel) {
case 0: case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg); gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired"; register_name = "Wired";
break; break;
case 1: case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg); gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0"; register_name = "SRSConf0";
break; break;
case 2: case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg); gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1"; register_name = "SRSConf1";
break; break;
case 3: case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg); gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2"; register_name = "SRSConf2";
break; break;
case 4: case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg); gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3"; register_name = "SRSConf3";
break; break;
case 5: case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg); gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4"; register_name = "SRSConf4";
break; break;
case 6: case CP0_REG06__PWCTL:
check_pw(ctx); check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg); gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl"; register_name = "PWCtl";