mirror of https://github.com/proxmox/mirror_qemu
ppc/pnv: Add a HOMER model to POWER10
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>master
parent
623575e16c
commit
924996766b
20
hw/ppc/pnv.c
20
hw/ppc/pnv.c
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@ -1595,6 +1595,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
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object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
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object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
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object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
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object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
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object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
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object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
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object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
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if (defaults_enabled()) {
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if (defaults_enabled()) {
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chip->num_pecs = pcc->num_pecs;
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chip->num_pecs = pcc->num_pecs;
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@ -1731,6 +1732,25 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
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pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
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pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
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&chip10->occ.xscom_regs);
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&chip10->occ.xscom_regs);
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/* OCC SRAM model */
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memory_region_add_subregion(get_system_memory(),
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PNV10_OCC_SENSOR_BASE(chip),
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&chip10->occ.sram_regs);
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/* HOMER */
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object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
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&error_abort);
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if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
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return;
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}
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/* Homer Xscom region */
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pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
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&chip10->homer.pba_regs);
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/* Homer mmio region */
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memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
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&chip10->homer.regs);
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/* PHBs */
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/* PHBs */
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pnv_chip_power10_phb_realize(chip, &local_err);
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pnv_chip_power10_phb_realize(chip, &local_err);
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if (local_err) {
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if (local_err) {
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@ -332,6 +332,69 @@ static const TypeInfo pnv_homer_power9_type_info = {
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.class_init = pnv_homer_power9_class_init,
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.class_init = pnv_homer_power9_class_init,
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};
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};
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static uint64_t pnv_homer_power10_pba_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvHomer *homer = PNV_HOMER(opaque);
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PnvChip *chip = homer->chip;
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uint32_t reg = addr >> 3;
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uint64_t val = 0;
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switch (reg) {
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case PBA_BAR0:
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val = PNV10_HOMER_BASE(chip);
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break;
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case PBA_BARMASK0: /* P10 homer region mask */
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val = (PNV10_HOMER_SIZE - 1) & 0x300000;
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break;
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case PBA_BAR2: /* P10 occ common area */
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val = PNV10_OCC_COMMON_AREA_BASE;
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break;
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case PBA_BARMASK2: /* P10 occ common area size */
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val = (PNV10_OCC_COMMON_AREA_SIZE - 1) & 0x700000;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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return val;
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}
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static void pnv_homer_power10_pba_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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static const MemoryRegionOps pnv_homer_power10_pba_ops = {
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.read = pnv_homer_power10_pba_read,
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.write = pnv_homer_power10_pba_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_homer_power10_class_init(ObjectClass *klass, void *data)
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{
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PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
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homer->pba_size = PNV10_XSCOM_PBA_SIZE;
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homer->pba_ops = &pnv_homer_power10_pba_ops;
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homer->homer_size = PNV10_HOMER_SIZE;
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homer->homer_ops = &pnv_power9_homer_ops; /* TODO */
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homer->core_max_base = PNV9_CORE_MAX_BASE;
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}
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static const TypeInfo pnv_homer_power10_type_info = {
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.name = TYPE_PNV10_HOMER,
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.parent = TYPE_PNV_HOMER,
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.instance_size = sizeof(PnvHomer),
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.class_init = pnv_homer_power10_class_init,
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};
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static void pnv_homer_realize(DeviceState *dev, Error **errp)
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static void pnv_homer_realize(DeviceState *dev, Error **errp)
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{
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{
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PnvHomer *homer = PNV_HOMER(dev);
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PnvHomer *homer = PNV_HOMER(dev);
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@ -377,6 +440,7 @@ static void pnv_homer_register_types(void)
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type_register_static(&pnv_homer_type_info);
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type_register_static(&pnv_homer_type_info);
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type_register_static(&pnv_homer_power8_type_info);
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type_register_static(&pnv_homer_power8_type_info);
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type_register_static(&pnv_homer_power9_type_info);
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type_register_static(&pnv_homer_power9_type_info);
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type_register_static(&pnv_homer_power10_type_info);
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}
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}
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type_init(pnv_homer_register_types);
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type_init(pnv_homer_register_types);
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@ -129,6 +129,7 @@ struct Pnv10Chip {
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Pnv9Psi psi;
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Pnv9Psi psi;
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PnvLpcController lpc;
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PnvLpcController lpc;
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PnvOCC occ;
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PnvOCC occ;
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PnvHomer homer;
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uint32_t nr_quads;
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uint32_t nr_quads;
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PnvQuad *quads;
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PnvQuad *quads;
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@ -364,4 +365,13 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
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#define PNV10_XIVE2_END_SIZE 0x0000020000000000ull
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#define PNV10_XIVE2_END_SIZE 0x0000020000000000ull
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#define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
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#define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
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#define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull
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#define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \
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PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
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#define PNV10_HOMER_SIZE 0x0000000000400000ull
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#define PNV10_HOMER_BASE(chip) \
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(0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)
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#endif /* PPC_PNV_H */
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#endif /* PPC_PNV_H */
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@ -32,6 +32,9 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV8_HOMER,
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#define TYPE_PNV9_HOMER TYPE_PNV_HOMER "-POWER9"
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#define TYPE_PNV9_HOMER TYPE_PNV_HOMER "-POWER9"
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DECLARE_INSTANCE_CHECKER(PnvHomer, PNV9_HOMER,
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DECLARE_INSTANCE_CHECKER(PnvHomer, PNV9_HOMER,
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TYPE_PNV9_HOMER)
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TYPE_PNV9_HOMER)
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#define TYPE_PNV10_HOMER TYPE_PNV_HOMER "-POWER10"
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DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER,
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TYPE_PNV10_HOMER)
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struct PnvHomer {
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struct PnvHomer {
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DeviceState parent;
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DeviceState parent;
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@ -134,6 +134,9 @@ struct PnvXScomInterfaceClass {
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#define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE
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#define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE
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#define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE
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#define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE
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#define PNV10_XSCOM_PBA_BASE 0x01010CDA
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#define PNV10_XSCOM_PBA_SIZE 0x40
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#define PNV10_XSCOM_XIVE2_BASE 0x2010800
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#define PNV10_XSCOM_XIVE2_BASE 0x2010800
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#define PNV10_XSCOM_XIVE2_SIZE 0x400
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#define PNV10_XSCOM_XIVE2_SIZE 0x400
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