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target-*: Increment num_insns immediately after tcg_gen_insn_start 

This does tidy the icount test common to all targets.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
master
Richard Henderson 2015-09-17 14:25:46 -07:00
parent 667b8e29c5
commit 959082fc4a
19 changed files with 41 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target-alpha/translate.c
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@ -2934,12 +2934,12 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(ctx.pc); tcg_gen_insn_start(ctx.pc);
num_insns++;
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
insn = cpu_ldl_code(env, ctx.pc); insn = cpu_ldl_code(env, ctx.pc);
num_insns++;
TCGV_UNUSED_I64(ctx.zero); TCGV_UNUSED_I64(ctx.zero);
TCGV_UNUSED_I64(ctx.sink); TCGV_UNUSED_I64(ctx.sink);

6
target-arm/translate-a64.c
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@ -11104,8 +11104,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(dc->pc); tcg_gen_insn_start(dc->pc);
num_insns++;
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
@ -11120,7 +11121,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
* "did not step an insn" case, and so the syndrome ISV and EX * "did not step an insn" case, and so the syndrome ISV and EX
* bits should be zero. * bits should be zero.
*/ */
assert(num_insns == 0); assert(num_insns == 1);
gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
default_exception_el(dc)); default_exception_el(dc));
dc->is_jmp = DISAS_EXC; dc->is_jmp = DISAS_EXC;
@ -11139,7 +11140,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
* Also stop translation when a page boundary is reached. This * Also stop translation when a page boundary is reached. This
* ensures prefetch aborts occur at the right place. * ensures prefetch aborts occur at the right place.
*/ */
num_insns++;
} while (!dc->is_jmp && !tcg_op_buf_full() && } while (!dc->is_jmp && !tcg_op_buf_full() &&
!cs->singlestep_enabled && !cs->singlestep_enabled &&
!singlestep && !singlestep &&

7
target-arm/translate.c
View File

@ -11349,9 +11349,11 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(dc->pc); tcg_gen_insn_start(dc->pc);
num_insns++;
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
}
if (dc->ss_active && !dc->pstate_ss) { if (dc->ss_active && !dc->pstate_ss) {
/* Singlestep state is Active-pending. /* Singlestep state is Active-pending.
@ -11364,7 +11366,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
* "did not step an insn" case, and so the syndrome ISV and EX * "did not step an insn" case, and so the syndrome ISV and EX
* bits should be zero. * bits should be zero.
*/ */
assert(num_insns == 0); assert(num_insns == 1);
gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
default_exception_el(dc)); default_exception_el(dc));
goto done_generating; goto done_generating;
@ -11400,7 +11402,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
* Otherwise the subsequent code could get translated several times. * Otherwise the subsequent code could get translated several times.
* Also stop translation when a page boundary is reached. This * Also stop translation when a page boundary is reached. This
* ensures prefetch aborts occur at the right place. */ * ensures prefetch aborts occur at the right place. */
num_insns ++;
} while (!dc->is_jmp && !tcg_op_buf_full() && } while (!dc->is_jmp && !tcg_op_buf_full() &&
!cs->singlestep_enabled && !cs->singlestep_enabled &&
!singlestep && !singlestep &&

4
target-cris/translate.c
View File

@ -3194,11 +3194,12 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(dc->pc); tcg_gen_insn_start(dc->pc);
num_insns++;
/* Pretty disas. */ /* Pretty disas. */
LOG_DIS("%8.8x:\t", dc->pc); LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
dc->clear_x = 1; dc->clear_x = 1;
@ -3210,7 +3211,6 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
cris_clear_x_flag(dc); cris_clear_x_flag(dc);
} }
num_insns++;
/* Check for delayed branches here. If we do it before /* Check for delayed branches here. If we do it before
actually generating any host code, the simulator will just actually generating any host code, the simulator will just
loop doing nothing for on this program location. */ loop doing nothing for on this program location. */

5
target-i386/translate.c
View File

@ -7960,12 +7960,13 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(pc_ptr); tcg_gen_insn_start(pc_ptr);
num_insns++;
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
}
pc_ptr = disas_insn(env, dc, pc_ptr); pc_ptr = disas_insn(env, dc, pc_ptr);
num_insns++;
/* stop translation if indicated */ /* stop translation if indicated */
if (dc->is_jmp) if (dc->is_jmp)
break; break;

5
target-lm32/translate.c
View File

@ -1103,18 +1103,17 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(dc->pc); tcg_gen_insn_start(dc->pc);
num_insns++;
/* Pretty disas. */ /* Pretty disas. */
LOG_DIS("%8.8x:\t", dc->pc); LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
decode(dc, cpu_ldl_code(env, dc->pc)); decode(dc, cpu_ldl_code(env, dc->pc));
dc->pc += 4; dc->pc += 4;
num_insns++;
} while (!dc->is_jmp } while (!dc->is_jmp
&& !tcg_op_buf_full() && !tcg_op_buf_full()
&& !cs->singlestep_enabled && !cs->singlestep_enabled

4
target-m68k/translate.c
View File

@ -3022,14 +3022,14 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(dc->pc); tcg_gen_insn_start(dc->pc);
num_insns++;
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
dc->insn_pc = dc->pc; dc->insn_pc = dc->pc;
disas_m68k_insn(env, dc); disas_m68k_insn(env, dc);
num_insns++;
} while (!dc->is_jmp && !tcg_op_buf_full() && } while (!dc->is_jmp && !tcg_op_buf_full() &&
!cs->singlestep_enabled && !cs->singlestep_enabled &&
!singlestep && !singlestep &&

5
target-microblaze/translate.c
View File

@ -1715,19 +1715,20 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(dc->pc); tcg_gen_insn_start(dc->pc);
num_insns++;
/* Pretty disas. */ /* Pretty disas. */
LOG_DIS("%8.8x:\t", dc->pc); LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
}
dc->clear_imm = 1; dc->clear_imm = 1;
decode(dc, cpu_ldl_code(env, dc->pc)); decode(dc, cpu_ldl_code(env, dc->pc));
if (dc->clear_imm) if (dc->clear_imm)
dc->tb_flags &= ~IMM_FLAG; dc->tb_flags &= ~IMM_FLAG;
dc->pc += 4; dc->pc += 4;
num_insns++;
if (dc->delayed_branch) { if (dc->delayed_branch) {
dc->delayed_branch--; dc->delayed_branch--;

5
target-mips/translate.c
View File

@ -19619,8 +19619,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(ctx.pc); tcg_gen_insn_start(ctx.pc);
num_insns++;
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
@ -19659,8 +19660,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
} }
ctx.pc += insn_bytes; ctx.pc += insn_bytes;
num_insns++;
/* Execute a branch and its delay slot as a single instruction. /* Execute a branch and its delay slot as a single instruction.
This is what GDB expects and is consistent with what the This is what GDB expects and is consistent with what the
hardware does (e.g. if a delay slot instruction faults, the hardware does (e.g. if a delay slot instruction faults, the

2
target-moxie/translate.c
View File

@ -862,10 +862,10 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(ctx.pc); tcg_gen_insn_start(ctx.pc);
num_insns++;
ctx.opcode = cpu_lduw_code(env, ctx.pc); ctx.opcode = cpu_lduw_code(env, ctx.pc);
ctx.pc += decode_opc(cpu, &ctx); ctx.pc += decode_opc(cpu, &ctx);
num_insns++;
if (cs->singlestep_enabled) { if (cs->singlestep_enabled) {
break; break;

4
target-openrisc/translate.c
View File

@ -1688,8 +1688,9 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
tcg_ctx.gen_opc_icount[k] = num_insns; tcg_ctx.gen_opc_icount[k] = num_insns;
} }
tcg_gen_insn_start(dc->pc); tcg_gen_insn_start(dc->pc);
num_insns++;
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
dc->ppc = dc->pc - 4; dc->ppc = dc->pc - 4;
@ -1698,7 +1699,6 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
tcg_gen_movi_tl(cpu_npc, dc->npc); tcg_gen_movi_tl(cpu_npc, dc->npc);
disas_openrisc_insn(dc, cpu); disas_openrisc_insn(dc, cpu);
dc->pc = dc->npc; dc->pc = dc->npc;
num_insns++;
/* delay slot */ /* delay slot */
if (dc->delayed_branch) { if (dc->delayed_branch) {
dc->delayed_branch--; dc->delayed_branch--;

4
target-ppc/translate.c
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@ -11503,11 +11503,12 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(ctx.nip); tcg_gen_insn_start(ctx.nip);
num_insns++;
LOG_DISAS("----------------\n"); LOG_DISAS("----------------\n");
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir); ctx.nip, ctx.mem_idx, (int)msr_ir);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start(); gen_io_start();
if (unlikely(need_byteswap(&ctx))) { if (unlikely(need_byteswap(&ctx))) {
ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
@ -11519,7 +11520,6 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
ctx.nip += 4; ctx.nip += 4;
table = env->opcodes; table = env->opcodes;
num_insns++;
handler = table[opc1(ctx.opcode)]; handler = table[opc1(ctx.opcode)];
if (is_indirect_opcode(handler)) { if (is_indirect_opcode(handler)) {
table = ind_table(handler); table = ind_table(handler);

3
target-s390x/translate.c
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@ -5371,8 +5371,9 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(dc.pc); tcg_gen_insn_start(dc.pc);
num_insns++;
if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }

4
target-sh4/translate.c
View File

@ -1873,14 +1873,14 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
tcg_ctx.gen_opc_icount[ii] = num_insns; tcg_ctx.gen_opc_icount[ii] = num_insns;
} }
tcg_gen_insn_start(ctx.pc); tcg_gen_insn_start(ctx.pc);
num_insns++;
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
ctx.opcode = cpu_lduw_code(env, ctx.pc); ctx.opcode = cpu_lduw_code(env, ctx.pc);
decode_opc(&ctx); decode_opc(&ctx);
num_insns++;
ctx.pc += 2; ctx.pc += 2;
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
break; break;

4
target-sparc/translate.c
View File

@ -5268,8 +5268,9 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
} }
} }
tcg_gen_insn_start(dc->pc); tcg_gen_insn_start(dc->pc);
num_insns++;
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
@ -5277,7 +5278,6 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
insn = cpu_ldl_code(env, dc->pc); insn = cpu_ldl_code(env, dc->pc);
disas_sparc_insn(dc, insn); disas_sparc_insn(dc, insn);
num_insns++;
if (dc->is_br) if (dc->is_br)
break; break;

3
target-tilegx/translate.c
View File

@ -2097,6 +2097,7 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(dc->pc); tcg_gen_insn_start(dc->pc);
num_insns++;
translate_one_bundle(dc, cpu_ldq_data(env, dc->pc)); translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
@ -2105,7 +2106,7 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
break; break;
} }
dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES; dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
if (++num_insns >= max_insns if (num_insns >= max_insns
|| dc->pc >= next_page_start || dc->pc >= next_page_start
|| tcg_op_buf_full()) { || tcg_op_buf_full()) {
/* Ending the TB due to TB size or page boundary. Set PC. */ /* Ending the TB due to TB size or page boundary. Set PC. */

3
target-tricore/translate.c
View File

@ -8293,12 +8293,11 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
gen_tb_start(tb); gen_tb_start(tb);
while (ctx.bstate == BS_NONE) { while (ctx.bstate == BS_NONE) {
tcg_gen_insn_start(ctx.pc); tcg_gen_insn_start(ctx.pc);
num_insns++;
ctx.opcode = cpu_ldl_code(env, ctx.pc); ctx.opcode = cpu_ldl_code(env, ctx.pc);
decode_opc(env, &ctx, 0); decode_opc(env, &ctx, 0);
num_insns++;
if (tcg_op_buf_full()) { if (tcg_op_buf_full()) {
gen_save_pc(ctx.next_pc); gen_save_pc(ctx.next_pc);
tcg_gen_exit_tb(0); tcg_gen_exit_tb(0);

4
target-unicore32/translate.c
View File

@ -1938,8 +1938,9 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
tcg_ctx.gen_opc_icount[lj] = num_insns; tcg_ctx.gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(dc->pc); tcg_gen_insn_start(dc->pc);
num_insns++;
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
@ -1958,7 +1959,6 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
* Otherwise the subsequent code could get translated several times. * Otherwise the subsequent code could get translated several times.
* Also stop translation when a page boundary is reached. This * Also stop translation when a page boundary is reached. This
* ensures prefetch aborts occur at the right place. */ * ensures prefetch aborts occur at the right place. */
num_insns++;
} while (!dc->is_jmp && !tcg_op_buf_full() && } while (!dc->is_jmp && !tcg_op_buf_full() &&
!cs->singlestep_enabled && !cs->singlestep_enabled &&
!singlestep && !singlestep &&

4
target-xtensa/translate.c
View File

@ -3077,10 +3077,11 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
tcg_ctx.gen_opc_icount[lj] = insn_count; tcg_ctx.gen_opc_icount[lj] = insn_count;
} }
tcg_gen_insn_start(dc.pc); tcg_gen_insn_start(dc.pc);
++insn_count;
++dc.ccount_delta; ++dc.ccount_delta;
if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start(); gen_io_start();
} }
@ -3101,7 +3102,6 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
} }
disas_xtensa_insn(env, &dc); disas_xtensa_insn(env, &dc);
++insn_count;
if (dc.icount) { if (dc.icount) {
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
} }