mirror of https://github.com/proxmox/mirror_qemu
Cleanup alpha memory ops prior to prctl PR_SET_UNALIGN
-----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmFnGJIdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8I2Qf/UOROm5TIvhKeZN8H t6zJCl+hcbCa9nsYHq38b+6+BNF2IAqMM+OJfGLfpSM+0QJJOsw8647qJUx4WVB6 VrOJ3HqRZnqk2rG1VUsnUjcg9r/C5VTFV1KE69d+M0WdW1lxw/ro3O0MW4trms6o X/TI1vI1lXF/MT4higfERYZTK6bRMpYllbkHYVq0u1lFSNvT+vfK9P/v4vPV5tNX GQfyvSDkGhxKYI/ZKosJflLBO3W67LubqVQUb8f+skowO2DLwnfqC0sDKd+q/Ar0 plF8vckI6sPUi1YxGwYAxxb/9lqTnshSH7BGBobLZWo/4vPJol7BHvisj82rmRXO C5iY7g== =3V2o -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20211013' into staging Cleanup alpha memory ops prior to prctl PR_SET_UNALIGN # gpg: Signature made Wed 13 Oct 2021 10:34:10 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-axp-20211013: target/alpha: Reorg integer memory operations target/alpha: Reorg fp memory operations Signed-off-by: Richard Henderson <richard.henderson@linaro.org>master
commit
984b2b5049
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@ -267,51 +267,51 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx)
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return gen_excp(ctx, EXCP_OPCDEC, 0);
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}
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static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
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static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
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{
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TCGv_i32 tmp32 = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);
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gen_helper_memory_to_f(t0, tmp32);
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tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
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gen_helper_memory_to_f(dest, tmp32);
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tcg_temp_free_i32(tmp32);
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}
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static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
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static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
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{
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TCGv tmp = tcg_temp_new();
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tcg_gen_qemu_ld_i64(tmp, t1, flags, MO_LEQ);
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gen_helper_memory_to_g(t0, tmp);
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tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
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gen_helper_memory_to_g(dest, tmp);
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tcg_temp_free(tmp);
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}
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static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
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static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr)
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{
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TCGv_i32 tmp32 = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);
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gen_helper_memory_to_s(t0, tmp32);
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tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
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gen_helper_memory_to_s(dest, tmp32);
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tcg_temp_free_i32(tmp32);
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}
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static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
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static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr)
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{
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tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL);
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tcg_gen_mov_i64(cpu_lock_addr, t1);
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tcg_gen_mov_i64(cpu_lock_value, t0);
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tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ);
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}
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static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
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static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
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void (*func)(DisasContext *, TCGv, TCGv))
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{
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tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ);
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tcg_gen_mov_i64(cpu_lock_addr, t1);
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tcg_gen_mov_i64(cpu_lock_value, t0);
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/* Loads to $f31 are prefetches, which we can treat as nops. */
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if (likely(ra != 31)) {
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TCGv addr = tcg_temp_new();
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tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
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func(ctx, cpu_fir[ra], addr);
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tcg_temp_free(addr);
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}
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}
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static inline void gen_load_mem(DisasContext *ctx,
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void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
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int flags),
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int ra, int rb, int32_t disp16, bool fp,
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bool clear)
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static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
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MemOp op, bool clear, bool locked)
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{
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TCGv tmp, addr, va;
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TCGv addr, dest;
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/* LDQ_U with ra $31 is UNOP. Other various loads are forms of
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prefetches, which we can treat as nops. No worries about
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@ -320,72 +320,75 @@ static inline void gen_load_mem(DisasContext *ctx,
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return;
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}
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tmp = tcg_temp_new();
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addr = load_gpr(ctx, rb);
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if (disp16) {
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tcg_gen_addi_i64(tmp, addr, disp16);
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addr = tmp;
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}
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addr = tcg_temp_new();
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tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
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if (clear) {
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tcg_gen_andi_i64(tmp, addr, ~0x7);
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addr = tmp;
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tcg_gen_andi_i64(addr, addr, ~0x7);
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}
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va = (fp ? cpu_fir[ra] : ctx->ir[ra]);
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tcg_gen_qemu_load(va, addr, ctx->mem_idx);
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dest = ctx->ir[ra];
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tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, op);
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tcg_temp_free(tmp);
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if (locked) {
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tcg_gen_mov_i64(cpu_lock_addr, addr);
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tcg_gen_mov_i64(cpu_lock_value, dest);
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}
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tcg_temp_free(addr);
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}
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static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
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static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr)
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{
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TCGv_i32 tmp32 = tcg_temp_new_i32();
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gen_helper_f_to_memory(tmp32, t0);
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tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);
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gen_helper_f_to_memory(tmp32, addr);
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tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
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tcg_temp_free_i32(tmp32);
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}
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static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
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static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr)
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{
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TCGv tmp = tcg_temp_new();
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gen_helper_g_to_memory(tmp, t0);
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tcg_gen_qemu_st_i64(tmp, t1, flags, MO_LEQ);
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gen_helper_g_to_memory(tmp, src);
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tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
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tcg_temp_free(tmp);
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}
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static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
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static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr)
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{
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TCGv_i32 tmp32 = tcg_temp_new_i32();
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gen_helper_s_to_memory(tmp32, t0);
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tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);
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gen_helper_s_to_memory(tmp32, src);
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tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
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tcg_temp_free_i32(tmp32);
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}
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static inline void gen_store_mem(DisasContext *ctx,
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void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
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int flags),
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int ra, int rb, int32_t disp16, bool fp,
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bool clear)
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static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr)
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{
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TCGv tmp, addr, va;
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tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ);
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}
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tmp = tcg_temp_new();
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addr = load_gpr(ctx, rb);
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static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
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void (*func)(DisasContext *, TCGv, TCGv))
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{
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TCGv addr = tcg_temp_new();
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tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
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func(ctx, load_fpr(ctx, ra), addr);
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tcg_temp_free(addr);
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}
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if (disp16) {
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tcg_gen_addi_i64(tmp, addr, disp16);
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addr = tmp;
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}
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static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
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MemOp op, bool clear)
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{
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TCGv addr, src;
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addr = tcg_temp_new();
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tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
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if (clear) {
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tcg_gen_andi_i64(tmp, addr, ~0x7);
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addr = tmp;
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tcg_gen_andi_i64(addr, addr, ~0x7);
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}
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va = (fp ? load_fpr(ctx, ra) : load_gpr(ctx, ra));
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tcg_gen_qemu_store(va, addr, ctx->mem_idx);
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src = load_gpr(ctx, ra);
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tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, op);
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tcg_temp_free(tmp);
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tcg_temp_free(addr);
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}
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static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
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@ -1480,30 +1483,30 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
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case 0x0A:
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/* LDBU */
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REQUIRE_AMASK(BWX);
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gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);
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gen_load_int(ctx, ra, rb, disp16, MO_UB, 0, 0);
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break;
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case 0x0B:
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/* LDQ_U */
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gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1);
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gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 1, 0);
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break;
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case 0x0C:
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/* LDWU */
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REQUIRE_AMASK(BWX);
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gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0);
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gen_load_int(ctx, ra, rb, disp16, MO_LEUW, 0, 0);
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break;
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case 0x0D:
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/* STW */
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REQUIRE_AMASK(BWX);
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gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0);
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gen_store_int(ctx, ra, rb, disp16, MO_LEUW, 0);
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break;
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case 0x0E:
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/* STB */
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REQUIRE_AMASK(BWX);
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gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0);
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gen_store_int(ctx, ra, rb, disp16, MO_UB, 0);
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break;
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case 0x0F:
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/* STQ_U */
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gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1);
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gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 1);
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break;
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case 0x10:
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@ -2458,11 +2461,15 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
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break;
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case 0x2:
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/* Longword physical access with lock (hw_ldl_l/p) */
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gen_qemu_ldl_l(va, addr, MMU_PHYS_IDX);
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tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL);
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tcg_gen_mov_i64(cpu_lock_addr, addr);
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tcg_gen_mov_i64(cpu_lock_value, va);
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break;
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case 0x3:
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/* Quadword physical access with lock (hw_ldq_l/p) */
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gen_qemu_ldq_l(va, addr, MMU_PHYS_IDX);
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tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEQ);
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tcg_gen_mov_i64(cpu_lock_addr, addr);
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tcg_gen_mov_i64(cpu_lock_value, va);
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break;
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case 0x4:
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/* Longword virtual PTE fetch (hw_ldl/v) */
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@ -2776,66 +2783,66 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
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case 0x20:
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/* LDF */
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REQUIRE_FEN;
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gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);
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gen_load_fp(ctx, ra, rb, disp16, gen_ldf);
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break;
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case 0x21:
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/* LDG */
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REQUIRE_FEN;
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gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0);
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gen_load_fp(ctx, ra, rb, disp16, gen_ldg);
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break;
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case 0x22:
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/* LDS */
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REQUIRE_FEN;
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gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0);
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gen_load_fp(ctx, ra, rb, disp16, gen_lds);
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break;
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case 0x23:
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/* LDT */
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REQUIRE_FEN;
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gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0);
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gen_load_fp(ctx, ra, rb, disp16, gen_ldt);
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break;
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case 0x24:
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/* STF */
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REQUIRE_FEN;
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gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0);
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gen_store_fp(ctx, ra, rb, disp16, gen_stf);
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break;
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case 0x25:
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/* STG */
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REQUIRE_FEN;
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gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0);
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gen_store_fp(ctx, ra, rb, disp16, gen_stg);
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break;
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case 0x26:
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/* STS */
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REQUIRE_FEN;
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gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0);
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gen_store_fp(ctx, ra, rb, disp16, gen_sts);
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break;
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case 0x27:
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/* STT */
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REQUIRE_FEN;
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gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0);
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gen_store_fp(ctx, ra, rb, disp16, gen_stt);
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break;
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case 0x28:
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/* LDL */
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gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0);
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gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 0);
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break;
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case 0x29:
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/* LDQ */
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gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0);
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gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 0);
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break;
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case 0x2A:
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/* LDL_L */
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gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0);
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gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 1);
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break;
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case 0x2B:
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/* LDQ_L */
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gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0);
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gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 1);
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break;
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case 0x2C:
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/* STL */
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gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0);
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gen_store_int(ctx, ra, rb, disp16, MO_LEUL, 0);
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break;
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case 0x2D:
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/* STQ */
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gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0);
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gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 0);
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break;
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case 0x2E:
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/* STL_C */
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Reference in New Issue